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PIC16F87XA Data Sheet
28/40-pin Enhanced FLASH Microcontrollers
2001 Microchip Technology Inc.
Advance Information
DS39582A
Note the following details of the code protection feature on PICmicro(R) MCUs. * * * The PICmicro family meets the specifications contained in the Microchip Data Sheet. Microchip believes that its family of PICmicro microcontrollers is one of the most secure products of its kind on the market today, when used in the intended manner and under normal conditions. There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our knowledge, require using the PICmicro microcontroller in a manner outside the operating specifications contained in the data sheet. The person doing so may be engaged in theft of intellectual property. Microchip is willing to work with the customer who is concerned about the integrity of their code. Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not mean that we are guaranteeing the product as "unbreakable". Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our product.
* * *
If you have any further questions about this matter, please contact the local sales office nearest to you.
Information contained in this publication regarding device applications and the like is intended through suggestion only and may be superseded by updates. It is your responsibility to ensure that your application meets with your specifications. No representation or warranty is given and no liability is assumed by Microchip Technology Incorporated with respect to the accuracy or use of such information, or infringement of patents or other intellectual property rights arising from such use or otherwise. Use of Microchip's products as critical components in life support systems is not authorized except with express written approval by Microchip. No licenses are conveyed, implicitly or otherwise, under any intellectual property rights.
Trademarks The Microchip name and logo, the Microchip logo, FilterLab, KEELOQ, MPLAB, PIC, PICmicro, PICMASTER, PICSTART, PRO MATE, SEEVAL and The Embedded Control Solutions Company are registered trademarks of Microchip Technology Incorporated in the U.S.A. and other countries. dsPIC, ECONOMONITOR, FanSense, FlexROM, fuzzyLAB, In-Circuit Serial Programming, ICSP, ICEPIC, microID, microPort, Migratable Memory, MPASM, MPLIB, MPLINK, MPSIM, MXDEV, PICC, PICDEM, PICDEM.net, rfPIC, Select Mode and Total Endurance are trademarks of Microchip Technology Incorporated in the U.S.A. Serialized Quick Term Programming (SQTP) is a service mark of Microchip Technology Incorporated in the U.S.A. All other trademarks mentioned herein are property of their respective companies. (c) 2001, Microchip Technology Incorporated, Printed in the U.S.A., All Rights Reserved.
Printed on recycled paper.
Microchip received QS-9000 quality system certification for its worldwide headquarters, design and wafer fabrication facilities in Chandler and Tempe, Arizona in July 1999. The Company's quality system processes and procedures are QS-9000 compliant for its PICmicro(R) 8-bit MCUs, KEELOQ(R) code hopping devices, Serial EEPROMs and microperipheral products. In addition, Microchip's quality system for the design and manufacture of development systems is ISO 9001 certified.
DS39582A - page ii
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2001 Microchip Technology Inc.
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* PIC16F873A * PIC16F874A
PIC16F87XA
Analog Features:
* 10-bit, up to 8 channel Analog-to-Digital Converter (A/D) * Brown-out Reset (BOR) * Analog Comparator module with: - Two analog comparators - Programmable on-chip voltage reference (VREF) module - Programmable input multiplexing from device inputs and internal voltage reference - Comparator outputs are externally accessible
28/40-Pin Enhanced FLASH Microcontrollers
Devices Included in this Data Sheet:
* PIC16F876A * PIC16F877A
High Performance RISC CPU:
* Only 35 single word instructions to learn * All single cycle instructions except for program branches, which are two-cycle * Operating speed: DC - 20 MHz clock input DC - 200 ns instruction cycle * Up to 8K x 14 words of FLASH Program Memory, Up to 368 x 8 bytes of Data Memory (RAM), Up to 256 x 8 bytes of EEPROM Data Memory * Pinout compatible to other 28-pin or 40/44-pin PIC16CXXX and PIC16FXXX microcontrollers
Special Microcontroller Features:
* 100,000 erase/write cycle Enhanced FLASH program memory typical * 1,000,000 erase/write cycle Data EEPROM memory typical * Data EEPROM Retention > 40 years * Self-reprogrammable under software control * In-Circuit Serial ProgrammingTM (ICSPTM) via two pins * Single supply 5V In-Circuit Serial Programming * Watchdog Timer (WDT) with its own on-chip RC oscillator for reliable operation * Programmable code protection * Power saving SLEEP mode * Selectable oscillator options * In-Circuit Debug (ICD) via two pins
Peripheral Features:
* Timer0: 8-bit timer/counter with 8-bit prescaler * Timer1: 16-bit timer/counter with prescaler, can be incremented during SLEEP via external crystal/clock * Timer2: 8-bit timer/counter with 8-bit period register, prescaler and postscaler * Two Capture, Compare, PWM modules - Capture is 16-bit, max. resolution is 12.5 ns - Compare is 16-bit, max. resolution is 200 ns - PWM max. resolution is 10-bit * Synchronous Serial Port (SSP) with SPITM (Master mode) and I2CTM (Master/Slave) * Universal Synchronous Asynchronous Receiver Transmitter (USART/SCI) with 9-bit address detection * Parallel Slave Port (PSP) 8-bits wide, with external RD, WR and CS controls (40/44-pin only) * Brown-out detection circuitry for Brown-out Reset (BOR)
CMOS Technology:
* * * * * Low power, high speed FLASH/EEPROM technology Fully static design Wide operating voltage range (2.0V to 5.5V) Commercial and Industrial temperature ranges Low power consumption
Device
MSSP Data EEPROM 10-bit CCP Timers SRAM I/O USART Comparators # Single Word (Bytes) A/D (ch) (PWM) SPI Master 8/16-bit Bytes (Bytes) 2 Instructions IC 7.2K 7.2K 4096 4096 8192 8192 192 192 368 368 128 128 256 256 22 33 22 33 5 8 5 8 2 2 2 2 Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes 2/1 2/1 2/1 2/1 2 2 2 2
Program Memory
PIC16F873A PIC16F874A
PIC16F876A 14.3K PIC16F877A 14.3K
2001 Microchip Technology Inc.
Advance Information
DS39582A-page 1
PIC16F87XA
Pin Diagrams
PDIP (28-pin), SOIC, SSOP
MCLR/VPP RA0/AN0 RA1/AN1 RA2/AN2/VREF-/CVREF RA3/AN3/VREF+ RA4/T0CKI/C1OUT RA5/AN4/SS/C2OUT VSS OSC1/CLKIN OSC2/CLKOUT RC0/T1OSO/T1CKI RC1/T1OSI/CCP2 RC2/CCP1 RC3/SCK/SCL 1 2 3 4 5 6 7 8 9 10 11 12 13 14 28 27 26 25 24 23 22 21 20 19 18 17 16 15 RB7/PGD RB6/PGC RB5 RB4 RB3/PGM RB2 RB1 RB0/INT VDD VSS RC7/RX/DT RC6/TX/CK RC5/SDO RC4/SDI/SDA
MLF
RA1/AN1 RA0/AN0 MCLR/VPP RB7/PGD RB6/PGC RB5 RB4 RA2/AN2/VREF-/CVREF RA3/AN3/VREF+ RA4/T0CKI/C1OUT RA5/AN4/SS/C2OUT VSS OSC1/CLKIN OSC2/CLKOUT 1 2 3 4 5 6 7 28 27 26 25 24 23 22 21 20 PIC16F873A 19 18 PIC16F876A 17 16 15 8 9 10 11 12 13 14
PIC16F876A/873A
RB3/PGM RB2 RB1 RB0/INT VDD VSS RC7/RX/DT
DS39582A-page 2
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RC0/T1OSO/T1CKI RC1/T1OSI/CCP2 RC2/CCP1 RC3/SCK/SCL RC4/SDI/SDA RC5/SDO RC6/TX/CK
2001 Microchip Technology Inc.
PIC16F87XA
Pin Diagram
PDIP (40 pin)
MCLR/VPP RA0/AN0 RA1/AN1 RA2/AN2/VREF-/CVREF RA3/AN3/VREF+ RA4/T0CKI/C1OUT RA5/AN4/SS/C2OUT RE0/RD/AN5 RE1/WR/AN6 RE2/CS/AN7 VDD VSS OSC1/CLKIN OSC2/CLKOUT RC0/T1OSO/T1CKI RC1/T1OSI/CCP2 RC2/CCP1 RC3/SCK/SCL RD0/PSP0 RD1/PSP1 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 RB7/PGD RB6/PGC RB5 RB4 RB3/PGM RB2 RB1 RB0/INT VDD VSS RD7/PSP7 RD6/PSP6 RD5/PSP5 RD4/PSP4 RC7/RX/DT RC6/TX/CK RC5/SDO RC4/SDI/SDA RD3/PSP3 RD2/PSP2
PIC16F87A7/874A
PLCC
6 5 4 3 2 1 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 9 RB3/PGM RB2 RB1 RB0/INT VDD VSS RD7/PSP7 RD6/PSP6 RD5/PSP5 RD4/PSP4 RC7/RX/DT
RC6/TX/CK RC5/SDO RC4/SDI/SDA RD3/PSP3 RD2/PSP2 RD1/PSP1 RD0/PSP0 RC3/SCK/SCL RC2/CCP1 RC1/T1OSI/CCP2 NC
QFP
44 43 42 41 40 39 38 37 36 35 34
2001 Microchip Technology Inc.
NC NC RB4 RB5 RB6/PGC RB7/PGD MCLR/VPP RA0/AN0 RA1/AN1 RA2/AN2/VREF-/CVREF RA3/AN3/VREF+
12 13 14 15 16 17 18 19 20 21 22
RC7/RX/DT RD4/PSP4 RD5/PSP5 RD6/PSP6 RD7/PSP7 VSS VDD RB0/INT RB1 RB2 RB3/PGM
1 2 3 4 5 6 7 8 9 10 11
PIC16F877A PIC16F874A
33 32 31 30 29 28 27 26 25 24 23
NC RC0/T1OSO/T1CKI OSC2/CLKOUT OSC1/CLKIN VSS VDD RE2/AN7/CS RE1/AN6/WR RE0/AN5/RD RA5/AN4/SS/C2OUT RA4/T0CKI/C1OUT
Advance Information
RC1/T1OSI/CCP2 RC2/CCP1 RC3/SCK/SCL RD0/PSP0 RD1/PSP1 RD2/PSP2 RD3/PSP3 RC4/SDI/SDA RC5/SDO RC6/TX/CK NC
18 19 20 21 22 23 24 25 26 27 282
RA4/T0CKI/C1OUT RA5/AN4/SS/C2OUT RE0/RD/AN5 RE1/WR/AN6 RE2/CS/AN7 VDD VSS OSC1/CLKIN OSC2/CLKOUT RC0/T1OSO/T1CK1 NC
7 8 9 10 11 12 13 14 15 16 17
RA3/AN3/VREF+ RA2/AN2/VREF-/CVREF RA1/AN1 RA0/AN0 MCLR/VPP NC RB7/PGD RB6/PGC RB5 RB4 NC
PIC16F877A PIC16F874A
DS39582A-page 3
PIC16F87XA
Table of Contents
1.0 Device Overview ......................................................................................................................................................................... 5 2.0 Memory Organization................................................................................................................................................................ 13 3.0 Data EEPROM and FLASH Program Memory ......................................................................................................................... 31 4.0 I/O Ports.................................................................................................................................................................................... 39 5.0 Timer0 Module .......................................................................................................................................................................... 51 6.0 Timer1 Module .......................................................................................................................................................................... 55 7.0 Timer2 Module .......................................................................................................................................................................... 59 8.0 Capture/Compare/PWM Modules ............................................................................................................................................. 61 9.0 Master Synchronous Serial Port (MSSP) Module..................................................................................................................... 69 10.0 Addressable Universal Synchronous Asynchronous Receiver Transmitter (USART) ............................................................ 109 11.0 Analog-to-Digital Converter (A/D) Module .............................................................................................................................. 125 12.0 Comparator Module ................................................................................................................................................................ 133 13.0 Comparator Voltage Reference Module ................................................................................................................................. 139 14.0 Special Features of the CPU .................................................................................................................................................. 141 15.0 Instruction Set Summary......................................................................................................................................................... 157 16.0 Development Support ............................................................................................................................................................. 165 17.0 Electrical Characteristics......................................................................................................................................................... 171 18.0 DC and AC Characteristics Graphs and Tables ..................................................................................................................... 195 19.0 Packaging Information ............................................................................................................................................................ 197 Appendix A: Revision History ........................................................................................................................................................ 207 Appendix B: Device Differences ..................................................................................................................................................... 207 Appendix C: Conversion Considerations ........................................................................................................................................ 208 Index ................................................................................................................................................................................................. 209 On-Line Support................................................................................................................................................................................ 217 Reader Response ............................................................................................................................................................................. 218 PIC16F87XA Product Identification System...................................................................................................................................... 219
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DS39582A-page 4
Advance Information
2001 Microchip Technology Inc.
PIC16F87XA
1.0 DEVICE OVERVIEW
This document contains device specific information about the following devices: * * * * PIC16F873A PIC16F874A PIC16F876A PIC16F877A The available features are summarized in Table 1-1. Block diagrams of the PIC16F873A/876A and PIC16F874A/877A devices are provided in Figure 1-1 and Figure 1-2, respectively. The pinouts for these device families are listed in Table 1-2 and Table 1-3. Additional information may be found in the PICmicroTM Mid-Range Reference Manual (DS33023), which may be obtained from your local Microchip Sales Representative or downloaded from the Microchip website. The Reference Manual should be considered a complementary document to this data sheet, and is highly recommended reading for a better understanding of the device architecture and operation of the peripheral modules.
PIC16F873A/876A devices are available only in 28-pin packages, while PIC16F874A/877A devices are available in 40-pin and 44-pin packages. All devices in the PIC16F87XA family share common architecture, with the following differences: * the PIC16F873A and PIC16F876A have one-half of the total on-chip memory of the PIC16F874A and PIC16F877A * the 28-pin devices have three I/O ports, while the 40/44-pin devices have five * the 28-pin devices have 14 interrupts, while the 40/44-pin devices have 15 * the 28-pin devices have five A/D input channels, while the 40/44-pin devices have eight * the Parallel Slave Port is implemented only on the 40/44-pin devices
TABLE 1-1:
PIC16F87XA DEVICE FEATURES
Key Features PIC16F873A DC - 20 MHz POR, BOR (PWRT, OST) 4K 192 128 14 Ports A,B,C 3 2 MSSP, USART -- 5 input channels 2 35 Instructions 28-pin PDIP 28-pin SOIC 28-pin SSOP 28-pin MLF PIC16F874A DC - 20 MHz POR, BOR (PWRT, OST) 4K 192 128 15 Ports A,B,C,D,E 3 2 MSSP, USART PSP 8 input channels 2 35 Instructions 40-pin PDIP 44-pin PLCC 44-pin QFP PIC16F876A DC - 20 MHz POR, BOR (PWRT, OST) 8K 368 256 14 Ports A,B,C 3 2 MSSP, USART -- 5 input channels 2 35 Instructions 28-pin PDIP 28-pin SOIC 28-pin SSOP 28-pin MLF PIC16F877A DC - 20 MHz POR, BOR (PWRT, OST) 8K 368 256 15 Ports A,B,C,D,E 3 2 MSSP, USART PSP 8 input channels 2 35 Instructions 40-pin PDIP 44-pin PLCC 44-pin QFP
Operating Frequency RESETS (and Delays) FLASH Program Memory (14-bit words) Data Memory (bytes) EEPROM Data Memory (bytes) Interrupts I/O Ports Timers Capture/Compare/PWM modules Serial Communications Parallel Communications 10-bit Analog-to-Digital Module Analog Comparators Instruction Set Packages
2001 Microchip Technology Inc.
Advance Information
DS39582A-page 5
PIC16F87XA
FIGURE 1-1: PIC16F873A/876A BLOCK DIAGRAM
13 Program Counter FLASH Program Memory Data Bus 8 PORTA RA0/AN0 RA1/AN1 RA2/AN2/VREF-/CVREF RA3/AN3/VREF+ RA4/T0CKI/C1OUT RA5/AN4/SS/C2OUT
8 Level Stack (13-bit)
RAM File Registers RAM Addr(1)
Program Bus
14 Instruction reg Direct Addr 7
9
Addr MUX 8 Indirect Addr PORTB RB0/INT RB1 RB2 RB3/PGM RB4 RB5 RB6/PGC RB7/PGD
FSR reg STATUS reg 8 3
Power-up Timer Instruction Decode & Control Timing Generation OSC1/CLKIN OSC2/CLKOUT Oscillator Start-up Timer Power-on Reset Watchdog Timer Brown-out Reset In-Circuit Debugger Low Voltage Programming 8
MUX
ALU PORTC W reg RC0/T1OSO/T1CKI RC1/T1OSI/CCP2 RC2/CCP1 RC3/SCK/SCL RC4/SDI/SDA RC5/SDO RC6/TX/CK RC7/RX/DT
MCLR
VDD, VSS
Timer0
Timer1
Timer2
10-bit A/D
Data EEPROM
CCP1,2
Synchronous Serial Port
USART
Comparator
Voltage Reference
Device PIC16F873A PIC16F876A
Program FLASH 4K words 8K words
Data Memory 192 Bytes 368 Bytes
Data EEPROM 128 Bytes 256 Bytes
Note 1: Higher order bits are from the STATUS register.
DS39582A-page 6
Advance Information
2001 Microchip Technology Inc.
PIC16F87XA
FIGURE 1-2: PIC16F874A/877A BLOCK DIAGRAM
13 Program Counter FLASH Program Memory 8 Level Stack (13-bit) RAM File Registers RAM Addr(1) 9 PORTB RB0/INT RB1 RB2 RB3/PGM RB4 RB5 RB6/PGC RB7/PGD PORTC Power-up Timer Instruction Decode & Control Timing Generation OSC1/CLKIN OSC2/CLKOUT Oscillator Start-up Timer Power-on Reset Watchdog Timer Brown-out Reset In-Circuit Debugger Low-Voltage Programming 8 W reg PORTD RD0/PSP0 RD1/PSP1 RD2/PSP2 RD3/PSP3 RD4/PSP4 RD5/PSP5 RD6/PSP6 RD7/PSP7 PORTE MCLR VDD, VSS RE0/AN5/RD RE1/AN6/WR RE2/AN7/CS 3 MUX RC0/T1OSO/T1CKI RC1/T1OSI/CCP2 RC2/CCP1 RC3/SCK/SCL RC4/SDI/SDA RC5/SDO RC6/TX/CK RC7/RX/DT Data Bus 8 PORTA RA0/AN0 RA1/AN1 RA2/AN2/VREF-/CVREF RA3/AN3/VREF+ RA4/T0CKI/C1OUT RA5/AN4/SS/C2OUT
Program Bus
14 Instruction reg Direct Addr 7
Addr MUX 8 Indirect Addr
FSR reg STATUS reg 8
ALU
Timer0
Timer1
Timer2
10-bit A/D
Parallel Slave Port
Data EEPROM
CCP1,2
Synchronous Serial Port
USART
Comparator
Voltage Reference
Device PIC16F874A PIC16F877A
Program FLASH 4K words 8K words
Data Memory 192 Bytes 368 Bytes
Data EEPROM 128 Bytes 256 Bytes
Note 1: Higher order bits are from the STATUS register.
2001 Microchip Technology Inc.
Advance Information
DS39582A-page 7
PIC16F87XA
TABLE 1-2:
Pin Name OSC1/CLKI OSC1 CLKI OSC2/CLKO OSC2 CLKO MCLR/VPP MCLR VPP RA0/AN0 RA0 AN0 RA1/AN1 RA1 AN1 RA2/AN2/VREF-/CVREF RA2 AN2 VREFCVREF RA3/AN3/VREF+ RA3 AN3 VREF+ RA4/T0CKI/C1OUT RA4 T0CKI C1OUT RA5/SS/AN4/C2OUT RA5 SS AN4 C2OUT Legend: 2 I/O I 3 I/O I 4 I/O I I O 5 I/O I I 6 I/O I O 7 I/O I I O TTL Digital I/O. SPI slave select input. Analog input 4. Comparator 2 output. ST Digital I/O - Open drain when configured as output. Timer0 external clock input. Comparator 1 output. TTL Digital I/O. Analog input 3. A/D reference voltage (High) input . TTL Digital I/O. Analog input 2. A/D reference voltage (Low) input. Comparator VREF output. TTL Digital I/O. Analog input 1. 1 I P TTL Digital I/O. Analog input 0. 10 O O ST
PIC16F873A/876A PINOUT DESCRIPTION
Pin# 9 I I I/O/P Type Buffer Type Description
ST/CMOS(3) Oscillator crystal or external clock input. Oscillator crystal input or external clock source input. ST buffer when configured in RC mode. Otherwise CMOS. External clock source input. Always associated with pin function OSC1 (see OSC1/CLKI, OSC2/CLKO pins). -- Oscillator crystal or clock output. Oscillator crystal output. Connects to crystal or resonator in Crystal Oscillator mode. In RC mode, OSC2 pin outputs CLKO, which has 1/4 the frequency of OSC1 and denotes the instruction cycle rate. Master Clear (input) or programming voltage (output) Master Clear (Reset) input. This pin is an active low RESET to the device. Programming voltage input. PORTA is a bi-directional I/O port.
I = input O = output I/O = input/output P = power -- = Not used TTL = TTL input ST = Schmitt Trigger input Note 1: This buffer is a Schmitt Trigger input when configured as the external interrupt. 2: This buffer is a Schmitt Trigger input when used in Serial Programming mode. 3: This buffer is a Schmitt Trigger input when configured in RC oscillator mode and a CMOS input otherwise.
DS39582A-page 8
Advance Information
2001 Microchip Technology Inc.
PIC16F87XA
TABLE 1-2:
Pin Name
PIC16F873A/876A PINOUT DESCRIPTION (CONTINUED)
Pin# I/O/P Type Buffer Type Description PORTB is a bi-directional I/O port. PORTB can be software programmed for internal weak pull-up on all inputs.
RB0/INT RB0 INT RB1 RB2 RB3/PGM RB3 PGM RB4 RB5 RB6/PGC RB6 PGC RB7/PGD RB7 PGD RC0/T1OSO/T1CKI RC0 T1OSO T1CKI RC1/T1OSI/CCP2 RC1 T1OSI CCP2 RC2/CCP1 RC2 CCP1 RC3/SCK/SCL RC3 SCK SCL RC4/SDI/SDA RC4 SDI SDA RC5/SDO RC5 SDO RC6/TX/CK RC6 TX CK RC7/RX/DT RC7 RX DT VSS VDD Legend:
21 I/O I 22 23 24 I/O I/O 25 26 27 I/O I/O 28 I/O I/O 11 I/O O I 12 I/O I I/O 13 I/O I/O 14 I/O I/O I/O 15 I/O I I/O 16 I/O O 17 I/O O I/O 18 I/O I I/O 8, 19 20 P P I/O I/O I/O I/O
TTL/ST(1) Digital I/O. External interrupt. TTL TTL TTL Digital I/O. Low voltage ICSP programming enable pin. TTL TTL TTL/ST(2) Digital I/O. In-Circuit Debugger and ICSP programming clock. TTL/ST(2) Digital I/O. In-Circuit Debugger and ICSP programming data. PORTC is a bi-directional I/O port. ST Digital I/O. Timer1 oscillator output. Timer1 external clock input. ST Digital I/O. Timer1 oscillator input. Capture2 input, Compare2 output, PWM2 output. ST Digital I/O. Capture1 input/Compare1 output/PWM1 output. ST Digital I/O. Synchronous serial clock input/output for SPI mode. Synchronous serial clock input/output for I2C mode. ST Digital I/O. SPI data in. I2C data I/O. ST Digital I/O. SPI data out. ST Digital I/O. USART asynchronous transmit. USART 1 synchronous clock. ST Digital I/O. USART asynchronous receive. USART synchronous data. -- -- Ground reference for logic and I/O pins. Positive supply for logic and I/O pins. Digital I/O. Digital I/O. Digital I/O. Digital I/O.
I = input O = output I/O = input/output P = power -- = Not used TTL = TTL input ST = Schmitt Trigger input Note 1: This buffer is a Schmitt Trigger input when configured as the external interrupt. 2: This buffer is a Schmitt Trigger input when used in Serial Programming mode. 3: This buffer is a Schmitt Trigger input when configured in RC oscillator mode and a CMOS input otherwise.
2001 Microchip Technology Inc.
Advance Information
DS39582A-page 9
PIC16F87XA
TABLE 1-3:
Pin Name OSC1/CLKI OSC1
PIC16F874A/877A PINOUT DESCRIPTION
DIP Pin# 13 PLCC Pin# 14 QFP Pin# 30 I/O/P Type I Buffer Type ST/CMOS(4) Description Oscillator crystal or external clock input. Oscillator crystal input or external clock source input. ST buffer when configured in RC mode. Otherwise CMOS. External clock source input. Always associated with pin function OSC1 (see OSC1/CLKI, OSC2/CLKO pins). Oscillator crystal or clock output. Oscillator crystal output. Connects to crystal or resonator in Crystal Oscillator mode. In RC mode, OSC2 pin outputs CLKO, which has 1/4 the frequency of OSC1 and denotes the instruction cycle rate. Master Clear (input) or programming voltage (output). Master Clear (Reset) input. This pin is an active low RESET to the device. Programming voltage input. PORTA is a bi-directional I/O port.
CLKI
OSC2/CLKOUT OSC2
14
15
31
O
--
CLKO
MCLR/VPP MCLR VPP RA0/AN0 RA0 AN0 RA1/AN1 RA1 AN1 RA2/AN2/VREF-/CVREF RA2 AN2 VREFCVREF RA3/AN3/VREF+ RA3 AN3 VREF+ RA4/T0CKI/C1OUT RA4 T0CKI C1OUT RA5/SS/AN4/C2OUT RA5 SS AN4 C2OUT Legend: I = input
1
2
18
I/P
ST
2
3
19 I/O I
TTL Digital I/O. Analog input 0. TTL I/O I Digital I/O. Analog input 1. TTL I/O I I O Digital I/O. Analog input 2. A/D reference voltage (Low) input. Comparator VREF output. TTL I/O I I Digital I/O. Analog input 3. A/D reference voltage (High) input. ST I/O I O Digital I/O - Open drain when configured as output. Timer0 external clock input. Comparator 1 output. TTL I/O I I O Digital I/O. SPI slave select input. Analog input 4. Comparator 2 output. P = power ST = Schmitt Trigger input
3
4
20
4
5
21
5
6
22
6
7
23
7
8
24
O = output -- = Not used
I/O = input/output TTL = TTL input
Note 1:This buffer is a Schmitt Trigger input when configured as an external interrupt. 2: This buffer is a Schmitt Trigger input when used in Serial Programming mode. 3: This buffer is a Schmitt Trigger input when configured as general purpose I/O and a TTL input when used in the Parallel Slave Port mode (for interfacing to a microprocessor bus). 4: This buffer is a Schmitt Trigger input when configured in RC oscillator mode and a CMOS input otherwise.
DS39582A-page 10
Advance Information
2001 Microchip Technology Inc.
PIC16F87XA
TABLE 1-3:
Pin Name
PIC16F874A/877A PINOUT DESCRIPTION (CONTINUED)
DIP Pin# PLCC Pin# QFP Pin# I/O/P Type Buffer Type Description PORTB is a bi-directional I/O port. PORTB can be software programmed for internal weak pull-up on all inputs.
RB0/INT RB0 INT RB1 RB2 RB3/PGM RB3 PGM RB4 RB5 RB6/PGC RB6 PGC RB7/PGD RB7 PGD RC0/T1OSO/T1CKI RC0 T1OSO T1CKI RC1/T1OSI/CCP2 RC1 T1OSI CCP2 RC2/CCP1 RC2 CCP1 RC3/SCK/SCL RC3 SCK SCL RC4/SDI/SDA RC4 SDI SDA RC5/SDO RC5 SDO RC6/TX/CK RC6 TX CK RC7/RX/DT RC7 RX DT Legend: I = input
33
36
8 I/O I
TTL/ST(1) Digital I/O. External interrupt. TTL TTL TTL I/O I/O Digital I/O. Low voltage ICSP programming enable pin. TTL TTL TTL/ST(2) I/O I/O Digital I/O. In-Circuit Debugger and ICSP programming clock. TTL/ST(2) I/O I/O Digital I/O. In-Circuit Debugger and ICSP programming data. PORTC is a bi-directional I/O port. ST I/O O I Digital I/O. Timer1 oscillator output. Timer1 external clock input. ST I/O I I/O Digital I/O. Timer1 oscillator input. Capture2 input, Compare2 output, PWM2 output. ST I/O I/O Digital I/O. Capture1 input/Compare1 output/PWM1 output. ST I/O I/O I/O Digital I/O. Synchronous serial clock input/output for SPI mode. Synchronous serial clock input/output for I2C mode. ST I/O I I/O Digital I/O. SPI data in. I2C data I/O. ST I/O O Digital I/O. SPI data out. ST I/O O I/O Digital I/O. USART asynchronous transmit. USART 1 synchronous clock. ST I/O I I/O Digital I/O. USART asynchronous receive. USART synchronous data. P = power ST = Schmitt Trigger input Digital I/O. Digital I/O. Digital I/O. Digital I/O.
34 35 36
37 38 39
9 10 11
I/O I/O
37 38 39
41 42 43
14 15 16
I/O I/O
40
44
17
15
16
32
16
18
35
17
19
36
18
20
37
23
25
42
24
26
43
25
27
44
26
29
1
O = output -- = Not used
I/O = input/output TTL = TTL input
Note 1:This buffer is a Schmitt Trigger input when configured as an external interrupt. 2: This buffer is a Schmitt Trigger input when used in Serial Programming mode. 3: This buffer is a Schmitt Trigger input when configured as general purpose I/O and a TTL input when used in the Parallel Slave Port mode (for interfacing to a microprocessor bus). 4: This buffer is a Schmitt Trigger input when configured in RC oscillator mode and a CMOS input otherwise.
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PIC16F87XA
TABLE 1-3:
Pin Name
PIC16F874A/877A PINOUT DESCRIPTION (CONTINUED)
DIP Pin# PLCC Pin# QFP Pin# I/O/P Type Buffer Type Description PORTD is a bi-directional I/O port or parallel slave port when interfacing to a microprocessor bus.
RD0/PSP0 RD0 PSP0 RD1/PSP1 RD1 PSP1 RD2/PSP2 RD2 PSP2 RD3/PSP3 RD3 PSP3 RD4/PSP4 RD4 PSP4 RD5/PSP5 RD5 PSP5 RD6/PSP6 RD6 PSP6 RD7/PSP7 RD7 PSP7 RE0/RD/AN5 RE0 RD AN5 RE1/WR/AN6 RE1 WR AN6 RE2/CS/AN7 RE2 CS AN7 VSS VDD NC Legend: I = input
19
21
38 I/O I/O
ST/TTL(3) Digital I/O. Parallel Slave Port data. ST/TTL(3) I/O I/O Digital I/O. Parallel Slave Port data. ST/TTL(3) I/O I/O Digital I/O. Parallel Slave Port data. ST/TTL(3) I/O I/O Digital I/O. Parallel Slave Port data. ST/TTL(3) I/O I/O Digital I/O. Parallel Slave Port data. ST/TTL(3) I/O I/O Digital I/O. Parallel Slave Port data. ST/TTL(3) I/O I/O Digital I/O. Parallel Slave Port data. ST/TTL(3) I/O I/O Digital I/O. Parallel Slave Port data. PORTE is a bi-directional I/O port. ST/TTL(3) I/O I I Digital I/O. Read control for parallel slave port. Analog input 5. ST/TTL(3) I/O I I Digital I/O. Write control for parallel slave port. Analog input 6. ST/TTL(3) I/O I I Digital I/O. Chip select control for parallel slave port. Analog input 7. -- -- -- Ground reference for logic and I/O pins. Positive supply for logic and I/O pins. These pins are not internally connected. These pins should be left unconnected. P = power ST = Schmitt Trigger input
20
22
39
21
23
40
22
24
41
27
30
2
28
31
3
29
32
4
30
33
5
8
9
25
9
10
26
10
11
27
12,31 11,32 --
13,34 12,35 1,17, 28,40
6,29 7,28 12,13, 33,34
P P
O = output -- = Not used
I/O = input/output TTL = TTL input
Note 1:This buffer is a Schmitt Trigger input when configured as an external interrupt. 2: This buffer is a Schmitt Trigger input when used in Serial Programming mode. 3: This buffer is a Schmitt Trigger input when configured as general purpose I/O and a TTL input when used in the Parallel Slave Port mode (for interfacing to a microprocessor bus). 4: This buffer is a Schmitt Trigger input when configured in RC oscillator mode and a CMOS input otherwise.
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2.0 MEMORY ORGANIZATION
2.1 Program Memory Organization
There are three memory blocks in each of the PIC16F87XA devices. The Program Memory and Data Memory have separate buses so that concurrent access can occur and is detailed in this section. The EEPROM data memory block is detailed in Section 3.0. Additional information on device memory may be found in the PICmicro Mid-Range Reference Manual (DS33023). The PIC16F87XA devices have a 13-bit program counter capable of addressing an 8K word x 14 bit program memory space. The PIC16F876A/877A devices have 8K words x 14 bits of FLASH program memory, while PIC16F873A/874A devices have 4K words x 14 bits. Accessing a location above the physically implemented address will cause a wraparound. The RESET vector is at 0000h and the interrupt vector is at 0004h.
FIGURE 2-1:
PIC16F876A/877A PROGRAM MEMORY MAP AND STACK
PC<12:0>
FIGURE 2-2:
PIC16F873A/874A PROGRAM MEMORY MAP AND STACK
PC<12:0>
CALL, RETURN RETFIE, RETLW
13
CALL, RETURN RETFIE, RETLW
13
Stack Level 1 Stack Level 2
Stack Level 1 Stack Level 2
Stack Level 8
Stack Level 8
RESET Vector
0000h
RESET Vector
0000h
Interrupt Vector
0004h 0005h
Interrupt Vector
0004h 0005h
Page 0
07FFh 0800h
On-Chip Program Memory
Page 0
07FFh 0800h
Page 1 On-Chip Program Memory Page 2
17FFh 1800h 0FFFh 1000h
Page 1
0FFFh 1000h
Page 3
1FFFh 1FFFh
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PIC16F87XA
2.2 Data Memory Organization
The data memory is partitioned into multiple banks which contain the General Purpose Registers and the Special Function Registers. Bits RP1 (STATUS<6>) and RP0 (STATUS<5>) are the bank select bits. RP1:RP0 00 01 10 11 Bank 0 1 2 3 Each bank extends up to 7Fh (128 bytes). The lower locations of each bank are reserved for the Special Function Registers. Above the Special Function Registers are General Purpose Registers, implemented as static RAM. All implemented banks contain Special Function Registers. Some frequently used Special Function Registers from one bank may be mirrored in another bank for code reduction and quicker access. Note: EEPROM Data Memory description can be found in Section 4.0 of this data sheet.
2.2.1
GENERAL PURPOSE REGISTER FILE
The register file can be accessed either directly, or indirectly through the File Select Register (FSR).
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FIGURE 2-3: PIC16F876A/877A REGISTER FILE MAP
File Address Indirect addr.(*) TMR0 PCL STATUS FSR PORTA PORTB PORTC PORTD(1) PORTE(1) PCLATH INTCON PIR1 PIR2 TMR1L TMR1H T1CON TMR2 T2CON SSPBUF SSPCON CCPR1L CCPR1H CCP1CON RCSTA TXREG RCREG CCPR2L CCPR2H CCP2CON ADRESH ADCON0 00h 01h 02h 03h 04h 05h 06h 07h 08h 09h 0Ah 0Bh 0Ch 0Dh 0Eh 0Fh 10h 11h 12h 13h 14h 15h 16h 17h 18h 19h 1Ah 1Bh 1Ch 1Dh 1Eh 1Fh 20h Indirect addr.(*) OPTION_REG PCL STATUS FSR TRISA TRISB TRISC TRISD(1) TRISE(1) PCLATH INTCON PIE1 PIE2 PCON File Address 80h 81h 82h 83h 84h 85h 86h 87h 88h 89h 8Ah 8Bh 8Ch 8Dh 8Eh 8Fh 90h 91h 92h 93h 94h 95h 96h 97h 98h 99h 9Ah 9Bh 9Ch 9Dh 9Eh 9Fh A0h General Purpose Register 80 Bytes accesses 70h-7Fh 7Fh Bank 0 Bank 1 General Purpose Register 80 Bytes accesses 70h-7Fh Bank 2 Indirect addr.(*) TMR0 PCL STATUS FSR PORTB File Address 100h 101h 102h 103h 104h 105h 106h 107h 108h 109h 10Ah 10Bh 10Ch 10Dh 10Eh 10Fh 110h 111h 112h 113h 114h 115h 116h 117h 118h 119h 11Ah 11Bh 11Ch 11Dh 11Eh 11Fh 120h Indirect addr.(*) OPTION_REG PCL STATUS FSR TRISB File Address 180h 181h 182h 183h 184h 185h 186h 187h 188h 189h 18Ah 18Bh 18Ch 18Dh 18Eh 18Fh 190h 191h 192h 193h 194h 195h 196h 197h 198h 199h 19Ah 19Bh 19Ch 19Dh 19Eh 19Fh 1A0h
PCLATH INTCON EEDATA EEADR EEDATH EEADRH
PCLATH INTCON EECON1 EECON2 Reserved(2) Reserved(2)
SSPCON2 PR2 SSPADD SSPSTAT
TXSTA SPBRG
General Purpose Register 16 Bytes
General Purpose Register 16 Bytes
CMCON CVRCON ADRESL ADCON1
General Purpose Register 96 Bytes
EFh F0h FFh
16Fh 170h 17Fh
General Purpose Register 80 Bytes accesses 70h - 7Fh Bank 3
1EFh 1F0h 1FFh
Unimplemented data memory locations, read as '0'. * Not a physical register. Note 1: These registers are not implemented on the PIC16F876A. 2: These registers are reserved, maintain these registers clear.
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PIC16F87XA
FIGURE 2-4: PIC16F873A/874A REGISTER FILE MAP
File Address Indirect addr.(*) TMR0 PCL STATUS FSR PORTA PORTB PORTC PORTD(1) PORTE(1) PCLATH INTCON PIR1 PIR2 TMR1L TMR1H T1CON TMR2 T2CON SSPBUF SSPCON CCPR1L CCPR1H CCP1CON RCSTA TXREG RCREG CCPR2L CCPR2H CCP2CON ADRESH ADCON0 00h 01h 02h 03h 04h 05h 06h 07h 08h 09h 0Ah 0Bh 0Ch 0Dh 0Eh 0Fh 10h 11h 12h 13h 14h 15h 16h 17h 18h 19h 1Ah 1Bh 1Ch 1Dh 1Eh 1Fh 20h File Address Indirect addr.(*) OPTION_REG PCL STATUS FSR TRISA TRISB TRISC TRISD(1) TRISE(1) PCLATH INTCON PIE1 PIE2 PCON 80h 81h 82h 83h 84h 85h 86h 87h 88h 89h 8Ah 8Bh 8Ch 8Dh 8Eh 8Fh 90h 91h 92h 93h 94h 95h 96h 97h 98h 99h 9Ah 9Bh 9Ch 9Dh 9Eh 9Fh A0h General Purpose Register 96 Bytes File Address Indirect addr.(*) 100h 101h TMR0 102h PCL 103h STATUS 104h FSR 105h 106h PORTB 107h 108h 109h 10Ah PCLATH 10Bh INTCON 10Ch EEDATA EEADR 10Dh 10Eh EEDATH 10Fh EEADRH 110h File Address Indirect addr.(*) OPTION_REG PCL STATUS FSR TRISB 180h 181h 182h 183h 184h 185h 186h 187h 188h 189h 18Ah 18Bh 18Ch 18Dh 18Eh 18Fh 190h
PCLATH INTCON EECON1 EECON2 Reserved(2) Reserved(2)
SSPCON2 PR2 SSPADD SSPSTAT
TXSTA SPBRG
CMCON CVRCON ADRESL ADCON1
120h
1A0h
General Purpose Register 96 Bytes
accesses 20h-7Fh 16Fh 170h FFh 17Fh Bank 2
accesses A0h - FFh 1EFh 1F0h 1FFh Bank 3
7Fh Bank 0 Bank 1
Unimplemented data memory locations, read as '0'. * Not a physical register. Note 1: These registers are not implemented on the PIC16F873A. 2: These registers are reserved, maintain these registers clear.
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2.2.2 SPECIAL FUNCTION REGISTERS
The Special Function Registers are registers used by the CPU and peripheral modules for controlling the desired operation of the device. These registers are implemented as static RAM. A list of these registers is given in Table 2-1. The Special Function Registers can be classified into two sets: core (CPU) and peripheral. Those registers associated with the core functions are described in detail in this section. Those related to the operation of the peripheral features are described in detail in the peripheral features section.
TABLE 2-1:
Address Bank 0 00h(3) 01h 02h
(3)
SPECIAL FUNCTION REGISTER SUMMARY
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on: POR, BOR Details on page:
Name
INDF TMR0 PCL STATUS FSR PORTA PORTB PORTC PORTD PORTE PCLATH INTCON PIR1 PIR2 TMR1L TMR1H T1CON TMR2 T2CON SSPBUF SSPCON CCPR1L CCPR1H CCP1CON RCSTA TXREG RCREG CCPR2L CCPR2H CCP2CON ADRESH ADCON0
Addressing this location uses contents of FSR to address data memory (not a physical register) 0000 0000 29, 148 Timer0 Module Register Program Counter (PC) Least Significant Byte IRP -- RP1 -- RP0 TO PD Z DC C Indirect Data Memory Address Pointer PORTA Data Latch when written: PORTA pins when read PORTB Data Latch when written: PORTB pins when read PORTC Data Latch when written: PORTC pins when read PORTD Data Latch when written: PORTD pins when read -- -- GIE PSPIF(3) -- -- -- PEIE ADIF CMIF -- -- TMR0IE RCIF -- -- INTE TXIF EEIF -- RBIE SSPIF BCLIF RE2 TMR0IF CCP1IF -- RE1 INTF TMR2IF -- RE0 RBIF TMR1IF CCP2IF Write Buffer for the upper 5 bits of the Program Counter
xxxx xxxx 53, 148 0000 0000 28, 148 0001 1xxx 20, 148 xxxx xxxx 29, 148 --0x 0000 41, 148 xxxx xxxx 43, 148 xxxx xxxx 45, 148 xxxx xxxx 46, 148 ---- -xxx 47, 148 ---0 0000 28, 148 0000 000x 22, 148 0000 0000 24, 148 -0-0 0--0 26, 148 xxxx xxxx 58, 148 xxxx xxxx 58, 148 0000 0000 60, 148
03h(3) 04h(3) 05h 06h 07h 08h(4) 09h
(4)
0Ah(1,3) 0Bh(3) 0Ch 0Dh 0Eh 0Fh 10h 11h 12h 13h 14h 15h 16h 17h 18h 19h 1Ah 1Bh 1Ch 1Dh 1Eh 1Fh
Holding register for the Least Significant Byte of the 16-bit TMR1 Register Holding register for the Most Significant Byte of the 16-bit TMR1 Register -- -- WCOL -- T1CKPS1 T1CKPS0 T1OSCEN T1SYNC Timer2 Module Register TOUTPS3 TOUTPS2 TOUTPS1 TOUTPS0 SSPOV SSPEN CKP SSPM3 Synchronous Serial Port Receive Buffer/Transmit Register SSPM2 SSPM1 SSPM0
TMR1CS TMR1ON --00 0000 55, 148
TMR2ON T2CKPS1 T2CKPS0 -000 0000 59, 148
xxxx xxxx 77, 148 0000 0000
71, 80, 148
Capture/Compare/PWM Register1 (LSB) Capture/Compare/PWM Register1 (MSB) -- SPEN -- RX9 CCP1X SREN CCP1Y CREN CCP1M3 ADDEN CCP1M2 FERR OERR RX9D
xxxx xxxx 61, 148 xxxx xxxx 61, 148
CCP1M1 CCP1M0 --00 0000 62, 148
0000 000x 110, 148 0000 0000 116, 148 0000 0000 116, 148 xxxx xxxx 61, 148 xxxx xxxx 61, 148
USART Transmit Data Register USART Receive Data Register Capture/Compare/PWM Register2 (LSB) Capture/Compare/PWM Register2 (MSB) -- ADCS1 -- ADCS0 CCP2X CHS2 CCP2Y CHS1 CCP2M3 CHS0 CCP2M2 GO/DONE A/D Result Register High Byte -- ADON
CCP2M1 CCP2M0 --00 0000 62, 148
xxxx xxxx 131, 148 0000 00-0 125, 148
Legend: x = unknown, u = unchanged, q = value depends on condition, - = unimplemented, read as '0', r = reserved. Shaded locations are unimplemented, read as `0'. Note 1: The upper byte of the program counter is not directly accessible. PCLATH is a holding register for the PC<12:8>, whose contents are transferred to the upper byte of the program counter. 2: Bits PSPIE and PSPIF are reserved on PIC16F873A/876A devices; always maintain these bits clear. 3: These registers can be addressed from any bank. 4: PORTD, PORTE, TRISD, and TRISE are not implemented on PIC16F873A/876A devices, read as `0'. 5: Bit 4 of EEADRH implemented only on the PIC16F876A/877A devices.
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PIC16F87XA
TABLE 2-1:
Address Bank 1 80h(3) 81h 82h(3) 83h(3) 84h(3) 85h 86h 87h 88h(4) 89h(4) 8Ah
(1,3)
SPECIAL FUNCTION REGISTER SUMMARY (CONTINUED)
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on: POR, BOR Details on page:
Name
INDF OPTION_REG PCL STATUS FSR TRISA TRISB TRISC TRISD TRISE PCLATH INTCON PIE1 PIE2 PCON -- -- SSPCON2 PR2 SSPADD SSPSTAT -- -- -- TXSTA SPBRG -- -- CMCON CVRCON ADRESL ADCON1
Addressing this location uses contents of FSR to address data memory (not a physical register) RBPU IRP -- INTEDG RP1 -- T0CS RP0 T0SE TO PSA PD PS2 Z PS1 DC PS0 C Program Counter (PC) Least Significant Byte Indirect Data Memory Address Pointer PORTA Data Direction Register PORTB Data Direction Register PORTC Data Direction Register PORTD Data Direction Register IBF -- GIE PSPIE(2) -- -- OBF -- PEIE ADIE CMIE -- IBOV -- TMR0IE RCIE -- -- PSPMODE INTE TXIE EEIE -- -- RBIE SSPIE BCLIE -- PORTE Data Direction Bits TMR0IF CCP1IE -- -- INTF TMR2IE -- POR RBIF TMR1IE CCP2IE BOR Write Buffer for the upper 5 bits of the Program Counter
0000 0000 29, 148 1111 1111 21, 148 0000 0000 28, 148 0001 1xxx 20, 148 xxxx xxxx 29, 148 --11 1111 41, 148 1111 1111 43, 148 1111 1111 45, 148 1111 1111 46, 148 0000 -111 48, 148 ---0 0000 28, 148 0000 000x 22, 148 0000 0000 23, 149 -0-0 0--0 25, 149 ---- --qq 27, 149
8Bh(3) 8Ch 8Dh 8Eh 8Fh 90h 91h 92h 93h 94h 95h 96h 97h 98h 99h 9Ah 9Bh 9Ch 9Dh 9Eh 9Fh
Unimplemented Unimplemented GCEN ACKSTAT ACKDT ACKEN RCEN PEN RSEN SEN Timer2 Period Register Synchronous Serial Port (I2C mode) Address Register SMP CKE D/A P S R/W UA BF Unimplemented Unimplemented Unimplemented CSRC TX9 TXEN SYNC -- BRGH TRMT TX9D Baud Rate Generator Register Unimplemented Unimplemented C2OUT CVREN ADFM C1OUT CVROE ADCS2 C2INV CVRR -- C1INV -- -- CIS CVR3 PCFG3 CM2 CVR2 PCFG2 CM1 CVR1 PCFG1 CM0 CVR0 PCFG0
-- --
-- --
0000 0000 81, 149 1111 1111 60, 149 0000 0000 77, 149 0000 0000 77, 149
-- -- --
-- -- --
0000 -010 109, 149 0000 0000 111, 149
-- --
-- --
0000 0111 133, 149 000- 0000 139, 149 xxxx xxxx 131, 149 0--- 0000 126, 149
A/D Result Register Low Byte
Legend: x = unknown, u = unchanged, q = value depends on condition, - = unimplemented, read as '0', r = reserved. Shaded locations are unimplemented, read as `0'. Note 1: The upper byte of the program counter is not directly accessible. PCLATH is a holding register for the PC<12:8>, whose contents are transferred to the upper byte of the program counter. 2: Bits PSPIE and PSPIF are reserved on PIC16F873A/876A devices; always maintain these bits clear. 3: These registers can be addressed from any bank. 4: PORTD, PORTE, TRISD, and TRISE are not implemented on PIC16F873A/876A devices, read as `0'. 5: Bit 4 of EEADRH implemented only on the PIC16F876A/877A devices.
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TABLE 2-1:
Address Bank 2 100h(3) 101h 102h(3) 103h 105h 106h 107h 108h 109h 10Bh(3) 10Ch 10Dh 10Eh 10Fh Bank 3 180h(3) 181h 182h
(3) (3)
SPECIAL FUNCTION REGISTER SUMMARY (CONTINUED)
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on: POR, BOR Details on page:
Name
INDF TMR0 PCL STATUS FSR -- PORTB -- -- -- INTCON EEDATA EEADR EEDATH EEADRH INDF OPTION_REG PCL STATUS FSR -- TRISB -- -- -- INTCON EECON1 EECON2 -- --
Addressing this location uses contents of FSR to address data memory (not a physical register) Timer0 Module Register Program Counter's (PC) Least Significant Byte IRP RP1 RP0 TO PD Z DC C Indirect Data Memory Address Pointer Unimplemented PORTB Data Latch when written: PORTB pins when read Unimplemented Unimplemented Unimplemented -- GIE -- PEIE -- TMR0IE Write Buffer for the upper 5 bits of the Program Counter INTE RBIE TMR0IF INTF RBIF
0000 0000 29, 148 xxxx xxxx 53, 148 0000 0000 28, 148 0001 1xxx 20, 148 xxxx xxxx 29, 148
104h(3)
-- -- -- --
-- -- -- --
xxxx xxxx 43, 148
10Ah(1,3) PCLATH
---0 0000 28, 148 0000 000x 22, 148 xxxx xxxx 37, 149 xxxx xxxx 37, 149 --xx xxxx 37, 149 ---- xxxx 37, 149
EEPROM Data Register Low Byte EEPROM Address Register Low Byte -- -- -- -- EEPROM Data Register High Byte -- --
(5)
EEPROM Address Register High Byte
Addressing this location uses contents of FSR to address data memory (not a physical register) RBPU IRP INTEDG RP1 T0CS RP0 T0SE TO PSA PD PS2 Z PS1 DC PS0 C Program Counter (PC) Least Significant Byte Indirect Data Memory Address Pointer Unimplemented PORTB Data Direction Register Unimplemented Unimplemented Unimplemented -- GIE EEPGD -- PEIE -- -- TMR0IE -- Write Buffer for the upper 5 bits of the Program Counter INTE -- RBIE WRERR TMR0IF WREN INTF WR RBIF RD
0000 0000 29, 148 1111 1111 21, 148 0000 0000 28, 148 0001 1xxx 20, 148 xxxx xxxx 29, 148
183h(3) 184h(3) 185h 186h 187h 188h 189h 18Bh(3) 18Ch 18Dh 18Eh 18Fh
-- -- -- --
-- -- -- --
1111 1111 43, 148
18Ah(1,3) PCLATH
---0 0000 28, 148 0000 000x 22, 148 x--- x000 32, 149 ---- ---- 37, 149 0000 0000 0000 0000
EEPROM Control Register2 (not a physical register) Reserved maintain clear Reserved maintain clear
-- --
Legend: x = unknown, u = unchanged, q = value depends on condition, - = unimplemented, read as '0', r = reserved. Shaded locations are unimplemented, read as `0'. Note 1: The upper byte of the program counter is not directly accessible. PCLATH is a holding register for the PC<12:8>, whose contents are transferred to the upper byte of the program counter. 2: Bits PSPIE and PSPIF are reserved on PIC16F873A/876A devices; always maintain these bits clear. 3: These registers can be addressed from any bank. 4: PORTD, PORTE, TRISD, and TRISE are not implemented on PIC16F873A/876A devices, read as `0'. 5: Bit 4 of EEADRH implemented only on the PIC16F876A/877A devices.
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PIC16F87XA
2.2.2.1 STATUS Register
The STATUS register contains the arithmetic status of the ALU, the RESET status and the bank select bits for data memory. The STATUS register can be the destination for any instruction, as with any other register. If the STATUS register is the destination for an instruction that affects the Z, DC or C bits, then the write to these three bits is disabled. These bits are set or cleared according to the device logic. Furthermore, the TO and PD bits are not writable, therefore, the result of an instruction with the STATUS register as destination may be different than intended. For example, CLRF STATUS will clear the upper three bits and set the Z bit. This leaves the STATUS register as 000u u1uu (where u = unchanged). It is recommended, therefore, that only BCF, BSF, SWAPF and MOVWF instructions are used to alter the STATUS register, because these instructions do not affect the Z, C or DC bits from the STATUS register. For other instructions not affecting any status bits, see the "Instruction Set Summary." Note: The C and DC bits operate as a borrow and digit borrow bit, respectively, in subtraction. See the SUBLW and SUBWF instructions for examples.
REGISTER 2-1:
STATUS REGISTER (ADDRESS 03h, 83h, 103h, 183h)
R/W-0 IRP bit 7 R/W-0 RP1 R/W-0 RP0 R-1 TO R-1 PD R/W-x Z R/W-x DC R/W-x C bit 0
bit 7
IRP: Register Bank Select bit (used for indirect addressing) 1 = Bank 2, 3 (100h - 1FFh) 0 = Bank 0, 1 (00h - FFh) RP1:RP0: Register Bank Select bits (used for direct addressing) 11 = Bank 3 (180h - 1FFh) 10 = Bank 2 (100h - 17Fh) 01 = Bank 1 (80h - FFh) 00 = Bank 0 (00h - 7Fh) Each bank is 128 bytes TO: Time-out bit 1 = After power-up, CLRWDT instruction, or SLEEP instruction 0 = A WDT time-out occurred PD: Power-down bit 1 = After power-up or by the CLRWDT instruction 0 = By execution of the SLEEP instruction Z: Zero bit 1 = The result of an arithmetic or logic operation is zero 0 = The result of an arithmetic or logic operation is not zero DC: Digit carry/borrow bit (ADDWF, ADDLW,SUBLW,SUBWF instructions) (for borrow, the polarity is reversed) 1 = A carry-out from the 4th low order bit of the result occurred 0 = No carry-out from the 4th low order bit of the result C: Carry/borrow bit (ADDWF, ADDLW,SUBLW,SUBWF instructions) 1 = A carry-out from the Most Significant bit of the result occurred 0 = No carry-out from the Most Significant bit of the result occurred Note: For borrow, the polarity is reversed. A subtraction is executed by adding the two's complement of the second operand. For rotate (RRF, RLF) instructions, this bit is loaded with either the high, or low order bit of the source register.
bit 6-5
bit 4
bit 3
bit 2
bit 1
bit 0
Legend: R = Readable bit - n = Value at POR W = Writable bit '1' = Bit is set U = Unimplemented bit, read as `0' '0' = Bit is cleared x = Bit is unknown
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2.2.2.2 OPTION_REG Register
Note: The OPTION_REG Register is a readable and writable register, which contains various control bits to configure the TMR0 prescaler/WDT postscaler (single assignable register known also as the prescaler), the External INT Interrupt, TMR0 and the weak pull-ups on PORTB. To achieve a 1:1 prescaler assignment for the TMR0 register, assign the prescaler to the Watchdog Timer.
REGISTER 2-2:
OPTION_REG REGISTER (ADDRESS 81h, 181h)
R/W-1 RBPU bit 7 R/W-1 INTEDG R/W-1 T0CS R/W-1 T0SE R/W-1 PSA R/W-1 PS2 R/W-1 PS1 R/W-1 PS0 bit 0
bit 7
RBPU: PORTB Pull-up Enable bit 1 = PORTB pull-ups are disabled 0 = PORTB pull-ups are enabled by individual port latch values INTEDG: Interrupt Edge Select bit 1 = Interrupt on rising edge of RB0/INT pin 0 = Interrupt on falling edge of RB0/INT pin T0CS: TMR0 Clock Source Select bit 1 = Transition on RA4/T0CKI pin 0 = Internal instruction cycle clock (CLKOUT) T0SE: TMR0 Source Edge Select bit 1 = Increment on high-to-low transition on RA4/T0CKI pin 0 = Increment on low-to-high transition on RA4/T0CKI pin PSA: Prescaler Assignment bit 1 = Prescaler is assigned to the WDT 0 = Prescaler is assigned to the Timer0 module PS2:PS0: Prescaler Rate Select bits Bit Value 000 001 010 011 100 101 110 111 TMR0 Rate WDT Rate 1:2 1:4 1:8 1 : 16 1 : 32 1 : 64 1 : 128 1 : 256 1:1 1:2 1:4 1:8 1 : 16 1 : 32 1 : 64 1 : 128
bit 6
bit 5
bit 4
bit 3
bit 2-0
Legend: R = Readable bit - n = Value at POR Note: W = Writable bit '1' = Bit is set U = Unimplemented bit, read as `0' '0' = Bit is cleared x = Bit is unknown
When using low voltage ICSP programming (LVP) and the pull-ups on PORTB are enabled, bit 3 in the TRISB register must be cleared to disable the pull-up on RB3 and ensure the proper operation of the device
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PIC16F87XA
2.2.2.3 INTCON Register
Note: The INTCON Register is a readable and writable register, which contains various enable and flag bits for the TMR0 register overflow, RB Port change and External RB0/INT pin interrupts. Interrupt flag bits are set when an interrupt condition occurs, regardless of the state of its corresponding enable bit or the global enable bit, GIE (INTCON<7>). User software should ensure the appropriate interrupt flag bits are clear prior to enabling an interrupt.
REGISTER 2-3:
INTCON REGISTER (ADDRESS 0Bh, 8Bh, 10Bh, 18Bh)
R/W-0 GIE bit 7 R/W-0 PEIE R/W-0 TMR0IE R/W-0 INTE R/W-0 RBIE R/W-0 TMR0IF R/W-0 INTF R/W-x RBIF bit 0
bit 7
GIE: Global Interrupt Enable bit 1 = Enables all unmasked interrupts 0 = Disables all interrupts PEIE: Peripheral Interrupt Enable bit 1 = Enables all unmasked peripheral interrupts 0 = Disables all peripheral interrupts TMR0IE: TMR0 Overflow Interrupt Enable bit 1 = Enables the TMR0 interrupt 0 = Disables the TMR0 interrupt INTE: RB0/INT External Interrupt Enable bit 1 = Enables the RB0/INT external interrupt 0 = Disables the RB0/INT external interrupt RBIE: RB Port Change Interrupt Enable bit 1 = Enables the RB port change interrupt 0 = Disables the RB port change interrupt TMR0IF: TMR0 Overflow Interrupt Flag bit 1 = TMR0 register has overflowed (must be cleared in software) 0 = TMR0 register did not overflow INTF: RB0/INT External Interrupt Flag bit 1 = The RB0/INT external interrupt occurred (must be cleared in software) 0 = The RB0/INT external interrupt did not occur RBIF: RB Port Change Interrupt Flag bit 1 = At least one of the RB7:RB4 pins changed state; a mismatch condition will continue to set the bit. Reading PORTB will end the mismatch condition and allow the bit to be cleared (must be cleared in software). 0 = None of the RB7:RB4 pins have changed state Legend: R = Readable bit - n = Value at POR W = Writable bit '1' = Bit is set U = Unimplemented bit, read as `0' '0' = Bit is cleared x = Bit is unknown
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
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2.2.2.4 PIE1 Register
Note: The PIE1 register contains the individual enable bits for the peripheral interrupts. Bit PEIE (INTCON<6>) must be set to enable any peripheral interrupt.
REGISTER 2-4:
PIE1 REGISTER (ADDRESS 8Ch)
R/W-0 PSPIE bit 7
(1)
R/W-0 ADIE
R/W-0 RCIE
R/W-0 TXIE
R/W-0 SSPIE
R/W-0 CCP1IE
R/W-0 TMR2IE
R/W-0 TMR1IE bit 0
bit 7
PSPIE: Parallel Slave Port Read/Write Interrupt Enable bit(1) 1 = Enables the PSP read/write interrupt 0 = Disables the PSP read/write interrupt Note 1: PSPIE is reserved on PIC16F873A/876A devices; always maintain this bit clear.
bit 6
ADIE: A/D Converter Interrupt Enable bit 1 = Enables the A/D converter interrupt 0 = Disables the A/D converter interrupt RCIE: USART Receive Interrupt Enable bit 1 = Enables the USART receive interrupt 0 = Disables the USART receive interrupt TXIE: USART Transmit Interrupt Enable bit 1 = Enables the USART transmit interrupt 0 = Disables the USART transmit interrupt SSPIE: Synchronous Serial Port Interrupt Enable bit 1 = Enables the SSP interrupt 0 = Disables the SSP interrupt CCP1IE: CCP1 Interrupt Enable bit 1 = Enables the CCP1 interrupt 0 = Disables the CCP1 interrupt TMR2IE: TMR2 to PR2 Match Interrupt Enable bit 1 = Enables the TMR2 to PR2 match interrupt 0 = Disables the TMR2 to PR2 match interrupt TMR1IE: TMR1 Overflow Interrupt Enable bit 1 = Enables the TMR1 overflow interrupt 0 = Disables the TMR1 overflow interrupt
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
Legend: R = Readable bit - n = Value at POR W = Writable bit '1' = Bit is set U = Unimplemented bit, read as `0' '0' = Bit is cleared x = Bit is unknown
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PIC16F87XA
2.2.2.5 PIR1 Register
Note: The PIR1 register contains the individual flag bits for the peripheral interrupts. Interrupt flag bits are set when an interrupt condition occurs, regardless of the state of its corresponding enable bit or the global enable bit, GIE (INTCON<7>). User software should ensure the appropriate interrupt bits are clear prior to enabling an interrupt.
REGISTER 2-5:
PIR1 REGISTER (ADDRESS 0Ch)
R/W-0 PSPIF(1) bit 7 R/W-0 ADIF R-0 RCIF R-0 TXIF R/W-0 SSPIF R/W-0 CCP1IF R/W-0 TMR2IF R/W-0 TMR1IF bit 0
bit 7
PSPIF: Parallel Slave Port Read/Write Interrupt Flag bit(1) 1 = A read or a write operation has taken place (must be cleared in software) 0 = No read or write has occurred Note 1: PSPIF is reserved on PIC16F873A/876A devices; always maintain this bit clear. ADIF: A/D Converter Interrupt Flag bit 1 = An A/D conversion completed 0 = The A/D conversion is not complete RCIF: USART Receive Interrupt Flag bit 1 = The USART receive buffer is full 0 = The USART receive buffer is empty TXIF: USART Transmit Interrupt Flag bit 1 = The USART transmit buffer is empty 0 = The USART transmit buffer is full SSPIF: Synchronous Serial Port (SSP) Interrupt Flag bit 1 = The SSP interrupt condition has occurred, and must be cleared in software before returning from the Interrupt Service Routine. The conditions that will set this bit are: * SPI - A transmission/reception has taken place. * I2C Slave - A transmission/reception has taken place. * I2C Master - A transmission/reception has taken place. - The initiated START condition was completed by the SSP module. - The initiated STOP condition was completed by the SSP module. - The initiated Restart condition was completed by the SSP module. - The initiated Acknowledge condition was completed by the SSP module. - A START condition occurred while the SSP module was idle (Multi-Master system). - A STOP condition occurred while the SSP module was idle (Multi-Master system). 0 = No SSP interrupt condition has occurred CCP1IF: CCP1 Interrupt Flag bit Capture mode: 1 = A TMR1 register capture occurred (must be cleared in software) 0 = No TMR1 register capture occurred Compare mode: 1 = A TMR1 register compare match occurred (must be cleared in software) 0 = No TMR1 register compare match occurred PWM mode: Unused in this mode TMR2IF: TMR2 to PR2 Match Interrupt Flag bit 1 = TMR2 to PR2 match occurred (must be cleared in software) 0 = No TMR2 to PR2 match occurred TMR1IF: TMR1 Overflow Interrupt Flag bit 1 = TMR1 register overflowed (must be cleared in software) 0 = TMR1 register did not overflow Legend: R = Readable bit - n = Value at POR
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
W = Writable bit '1' = Bit is set
U = Unimplemented bit, read as `0' '0' = Bit is cleared x = Bit is unknown
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DS39582A-page 24
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PIC16F87XA
2.2.2.6 PIE2 Register
Note: The PIE2 register contains the individual enable bits for the CCP2 peripheral interrupt, the SSP bus collision interrupt, EEPROM write operation interrupt, and the comparator interrupt. Bit PEIE (INTCON<6>) must be set to enable any peripheral interrupt.
REGISTER 2-6:
PIE2 REGISTER (ADDRESS 8Dh)
U-0 -- bit 7 R/W-0 CMIE U-0 -- R/W-0 EEIE R/W-0 BCLIE U-0 -- U-0 -- R/W-0 CCP2IE bit 0
bit 7 bit 6
Unimplemented: Read as '0' CMIE: Comparator Interrupt Enable bit 1 = Enables the Comparator interrupt 0 = Disable the Comparator interrupt Unimplemented: Read as '0' EEIE: EEPROM Write Operation Interrupt Enable bit 1 = Enable EEPROM write interrupt 0 = Disable EEPROM write interrupt BCLIE: Bus Collision Interrupt Enable bit 1 = Enable bus collision interrupt 0 = Disable bus collision interrupt Unimplemented: Read as '0' CCP2IE: CCP2 Interrupt Enable bit 1 = Enables the CCP2 interrupt 0 = Disables the CCP2 interrupt Legend: R = Readable bit - n = Value at POR W = Writable bit '1' = Bit is set U = Unimplemented bit, read as `0' '0' = Bit is cleared x = Bit is unknown
bit 5 bit 4
bit 3
bit 2-1 bit 0
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PIC16F87XA
2.2.2.7 PIR2 Register
Note: The PIR2 register contains the flag bits for the CCP2 interrupt, the SSP bus collision interrupt, EEPROM write operation interrupt, and the comparator interrupt. Interrupt flag bits are set when an interrupt condition occurs, regardless of the state of its corresponding enable bit or the global enable bit, GIE (INTCON<7>). User software should ensure the appropriate interrupt flag bits are clear prior to enabling an interrupt.
REGISTER 2-7:
PIR2 REGISTER (ADDRESS 0Dh)
U-0 -- bit 7 R/W-0 CMIF U-0 -- R/W-0 EEIF R/W-0 BCLIF U-0 -- U-0 -- R/W-0 CCP2IF bit 0
bit 7 bit 6
Unimplemented: Read as '0' CMIF: Comparator Interrupt Flag bit 1 = The Comparator input has changed (must be cleared in software) 0 = The Comparator input has not changed Unimplemented: Read as '0' EEIF: EEPROM Write Operation Interrupt Flag bit 1 = The write operation completed (must be cleared in software) 0 = The write operation is not complete or has not been started BCLIF: Bus Collision Interrupt Flag bit 1 = A bus collision has occurred in the SSP, when configured for I2C Master mode 0 = No bus collision has occurred Unimplemented: Read as '0' CCP2IF: CCP2 Interrupt Flag bit Capture mode: 1 = A TMR1 register capture occurred (must be cleared in software) 0 = No TMR1 register capture occurred Compare mode: 1 = A TMR1 register compare match occurred (must be cleared in software) 0 = No TMR1 register compare match occurred PWM mode: Unused Legend: R = Readable bit - n = Value at POR W = Writable bit '1' = Bit is set U = Unimplemented bit, read as `0' '0' = Bit is cleared x = Bit is unknown
bit 5 bit 4
bit 3
bit 2-1 bit 0
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PIC16F87XA
2.2.2.8 PCON Register
Note: The Power Control (PCON) Register contains flag bits to allow differentiation between a Power-on Reset (POR), a Brown-out Reset (BOR), a Watchdog Reset (WDT), and an external MCLR Reset. BOR is unknown on Power-on Reset. It must be set by the user and checked on subsequent RESETS to see if BOR is clear, indicating a brown-out has occurred. The BOR status bit is a "don't care" and is not predictable if the brown-out circuit is disabled (by clearing the BODEN bit in the configuration word).
REGISTER 2-8:
PCON REGISTER (ADDRESS 8Eh)
U-0 -- bit 7 U-0 -- U-0 -- U-0 -- U-0 -- U-0 -- R/W-0 POR R/W-1 BOR bit 0
bit 7-2 bit 1
Unimplemented: Read as '0' POR: Power-on Reset Status bit 1 = No Power-on Reset occurred 0 = A Power-on Reset occurred (must be set in software after a Power-on Reset occurs) BOR: Brown-out Reset Status bit 1 = No Brown-out Reset occurred 0 = A Brown-out Reset occurred (must be set in software after a Brown-out Reset occurs) Legend: R = Readable bit - n = Value at POR W = Writable bit '1' = Bit is set U = Unimplemented bit, read as `0' '0' = Bit is cleared x = Bit is unknown
bit 0
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PIC16F87XA
2.3 PCL and PCLATH
The program counter (PC) is 13 bits wide. The low byte comes from the PCL register, which is a readable and writable register. The upper bits (PC<12:8>) are not readable, but are indirectly writable through the PCLATH register. On any RESET, the upper bits of the PC will be cleared. Figure 2-5 shows the two situations for the loading of the PC. The upper example in the figure shows how the PC is loaded on a write to PCL (PCLATH<4:0> PCH). The lower example in the figure shows how the PC is loaded during a CALL or GOTO instruction (PCLATH<4:3> PCH). Note 1: There are no status bits to indicate stack overflow or stack underflow conditions. 2: There are no instructions/mnemonics called PUSH or POP. These are actions that occur from the execution of the CALL, RETURN, RETLW and RETFIE instructions, or the vectoring to an interrupt address.
2.4
Program Memory Paging
FIGURE 2-5:
LOADING OF PC IN DIFFERENT SITUATIONS
PCL 8 7 0 Instruction with PCL as Destination ALU
PCH 12 PC 5
PCLATH<4:0>
8
PCLATH PCH 12 PC 2 PCLATH<4:3> 11 Opcode <10:0> PCLATH 11 10 8 7 PCL 0
GOTO,CALL
All PIC16F87XA devices are capable of addressing a continuous 8K word block of program memory. The CALL and GOTO instructions provide only 11 bits of address to allow branching within any 2K program memory page. When doing a CALL or GOTO instruction, the upper 2 bits of the address are provided by PCLATH<4:3>. When doing a CALL or GOTO instruction, the user must ensure that the page select bits are programmed so that the desired program memory page is addressed. If a return from a CALL instruction (or interrupt) is executed, the entire 13-bit PC is popped off the stack. Therefore, manipulation of the PCLATH<4:3> bits is not required for the return instructions (which POPs the address from the stack). Note: The contents of the PCLATH register are unchanged after a RETURN or RETFIE instruction is executed. The user must rewrite the contents of the PCLATH register for any subsequent subroutine calls or GOTO instructions.
2.3.1
COMPUTED GOTO
Example 2-1 shows the calling of a subroutine in page 1 of the program memory. This example assumes that PCLATH is saved and restored by the Interrupt Service Routine (if interrupts are used).
A computed GOTO is accomplished by adding an offset to the program counter (ADDWF PCL). When doing a table read using a computed GOTO method, care should be exercised if the table location crosses a PCL memory boundary (each 256 byte block). Refer to the application note, "Implementing a Table Read" (AN556).
EXAMPLE 2-1:
CALL OF A SUBROUTINE IN PAGE 1 FROM PAGE 0
ORG 0x500 BCF PCLATH,4 BSF PCLATH,3 CALL SUB1_P1 : : ORG 0x900 SUB1_P1 : : RETURN
2.3.2
STACK
;Select page 1 ;(800h-FFFh) ;Call subroutine in ;page 1 (800h-FFFh) ;page 1 (800h-FFFh) ;called subroutine ;page 1 (800h-FFFh) ;return to ;Call subroutine ;in page 0 ;(000h-7FFh)
The PIC16F87XA family has an 8-level deep x 13-bit wide hardware stack. The stack space is not part of either program or data space and the stack pointer is not readable or writable. The PC is PUSHed onto the stack when a CALL instruction is executed, or an interrupt causes a branch. The stack is POPed in the event of a RETURN, RETLW or a RETFIE instruction execution. PCLATH is not affected by a PUSH or POP operation. The stack operates as a circular buffer. This means that after the stack has been PUSHed eight times, the ninth push overwrites the value that was stored from the first push. The tenth push overwrites the second push (and so on).
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PIC16F87XA
2.5 Indirect Addressing, INDF and FSR Registers
A simple program to clear RAM locations 20h-2Fh using indirect addressing is shown in Example 2-2.
The INDF register is not a physical register. Addressing the INDF register will cause indirect addressing. Indirect addressing is possible by using the INDF register. Any instruction using the INDF register actually accesses the register pointed to by the File Select Register, FSR. Reading the INDF register itself, indirectly (FSR = '0') will read 00h. Writing to the INDF register indirectly results in a no operation (although status bits may be affected). An effective 9-bit address is obtained by concatenating the 8-bit FSR register and the IRP bit (STATUS<7>), as shown in Figure 2-6.
EXAMPLE 2-2:
MOVLW MOVWF CLRF INCF BTFSS GOTO :
INDIRECT ADDRESSING
0x20 FSR INDF FSR,F FSR,4 NEXT ;initialize pointer ;to RAM ;clear INDF register ;inc pointer ;all done? ;no clear next ;yes continue
NEXT
CONTINUE
FIGURE 2-6:
DIRECT/INDIRECT ADDRESSING
Direct Addressing Indirect Addressing 0 IRP 7 FSR register 0
RP1:RP0
6
From Opcode
Bank Select
Location Select 00 00h 01 80h 10 100h 11 180h
Bank Select
Location Select
Data Memory(1)
7Fh Bank 0
FFh Bank 1
17Fh Bank 2
1FFh Bank 3
Note 1: For register file map detail, see Figure 2-3.
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PIC16F87XA
NOTES:
DS39582A-page 30
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3.0 DATA EEPROM AND FLASH PROGRAM MEMORY
3.1 EEADR and EEADRH
The EEADRH:EEADR register pair can address up to a maximum of 256 bytes of data EEPROM or up to a maximum of 8K words of program EEPROM. When selecting a data address value, only the LSByte of the address is written to the EEADR register. When selecting a program address value, the MSByte of the address is written to the EEADRH register and the LSByte is written to the EEADR register. If the device contains less memory than the full address reach of the address register pair, the Most Significant bits of the registers are not implemented. For example, if the device has 128 bytes of data EEPROM, the Most Significant bit of EEADR is not implemented on access to data EEPROM.
The Data EEPROM and FLASH Program memory is readable and writable during normal operation (over the full VDD range). This memory is not directly mapped in the register file space. Instead, it is indirectly addressed through the Special Function Registers. There are six SFRs used to read and write this memory: * * * * * * EECON1 EECON2 EEDATA EEDATH EEADR EEADRH
When interfacing to the data memory block, EEDATA holds the 8-bit data for read/write, and EEADR holds the address of the EEPROM location being accessed. These devices have 128 or 256 bytes of data EEPROM (depending on the device), with an address range from 00h to FFh. On devices with 128 bytes, addresses from 80h to FFh are unimplemented and will wrap around to the beginning of data EEPROM memory. When writing to unimplemented locations, the on-chip charge pump will be turned off. When interfacing the program memory block, the EEDATA and EEDATH registers form a two-byte word that holds the 14-bit data for read/write, and the EEADR and EEADRH registers form a two-byte word that holds the 13-bit address of the program memory location being accessed. These devices have 4 or 8K words of program FLASH with an address range from 0000h to 0FFFh for the PIC16F873A/874A, and 0000h to 1FFFh for the PIC16F876A/877A. Addresses above the range of the respective device will wrap around to the beginning of program memory. The EEPROM data memory allows single byte read and write. The FLASH program memory allows single word reads and four-word block writes. Program memory write operations automatically perform an erasebefore-write on blocks of four words. A byte write in data EEPROM memory automatically erases the location and writes the new data (erase before write). The write time is controlled by an on-chip timer. The write/erase voltages are generated by an on chip charge pump, rated to operate over the voltage range of the device for byte or word operations. When the device is code protected, the CPU may continue to read and write the data EEPROM memory. Depending on the settings of the write protect bits, the device may or may not be able to write certain blocks of the program memory; however, reads of the program memory are allowed. When code protected, the device programmer can no longer access data or program memory; this does NOT inhibit internal reads or writes.
3.2
EECON1 and EECON2 Registers
EECON1 is the control register for memory accesses. Control bit EEPGD determines if the access will be a program or data memory access. When clear, as it is when reset, any subsequent operations will operate on the data memory. When set, any subsequent operations will operate on the program memory. Control bits RD and WR initiate read and write or erase, respectively. These bits cannot be cleared, only set, in software. They are cleared in hardware at completion of the read or write operation. The inability to clear the WR bit in software prevents the accidental, premature termination of a write operation. The WREN bit, when set, will allow a write or erase operation. On power-up, the WREN bit is clear. The WRERR bit is set when a write (or erase) operation is interrupted by a MCLR or a WDT Time-out Reset during normal operation. In these situations, following RESET, the user can check the WRERR bit and rewrite the location. The data and address will be unchanged in the EEDATA and EEADR registers. Interrupt flag bit EEIF in the PIR2 register is set when write is complete. It must be cleared in software. EECON2 is not a physical register. Reading EECON2 will read all '0's. The EECON2 register is used exclusively in the EEPROM write sequence.
Note:
The self-programming mechanism for FLASH program memory has been changed. On previous PIC16F87X devices, FLASH programming was done in single word erase/write cycles. The newer PIC16F87XA devices use a four-word erase/write cycle. See Section 3.6 for more information.
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PIC16F87XA
REGISTER 3-1: EECON1 REGISTER (ADDRESS 18Ch)
R/W-x EEPGD bit 7 bit 7 EEPGD: Program/Data EEPROM Select bit 1 = Accesses program memory 0 = Accesses data memory Reads `0' after a POR; this bit cannot be changed while a write operation is in progress. Unimplemented: Read as '0' WRERR: EEPROM Error Flag bit 1 = A write operation is prematurely terminated (any MCLR or any WDT Reset during normal operation) 0 = The write operation completed WREN: EEPROM Write Enable bit 1 = Allows write cycles 0 = Inhibits write to the EEPROM WR: Write Control bit 1 = Initiates a write cycle. The bit is cleared by hardware once write is complete. The WR bit can only be set (not cleared) in software. 0 = Write cycle to the EEPROM is complete RD: Read Control bit 1 = Initiates an EEPROM read; RD is cleared in hardware. The RD bit can only be set (not cleared) in software. 0 = Does not initiate an EEPROM read Legend: R = Readable bit - n = Value at POR W = Writable bit '1' = Bit is set U = Unimplemented bit, read as `0' '0' = Bit is cleared x = Bit is unknown U-0 -- U-0 -- U-0 -- R/W-x WRERR R/W-0 WREN R/S-0 WR R/S-0 RD bit 0
bit 6-4 bit 3
bit 2
bit 1
bit 0
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PIC16F87XA
3.3 Reading Data EEPROM Memory
The steps to write to EEPROM data memory are: 1. If step 10 is not implemented, check the WR bit to see if a write is in progress. 2. Write the address to EEADR. Make sure that the address is not larger than the memory size of the device. 3. Write the 8-bit data value to be programmed in the EEDATA register. 4. Clear the EEPGD bit to point to EEPROM data memory. 5. Set the WREN bit to enable program operations. 6. Disable interrupts (if enabled). 7. Execute the special five instruction sequence: * Write 55h to EECON2 in two steps (first to W, then to EECON2) * Write AAh to EECON2 in two steps (first to W, then to EECON2) * Set the WR bit 8. Enable interrupts (if using interrupts). 9. Clear the WREN bit to disable program operations. 10. At the completion of the write cycle, the WR bit is cleared and the EEIF interrupt flag bit is set. (EEIF must be cleared by firmware.) If step 1 is not implemented, then firmware should check for EEIF to be set, or WR to clear, to indicate the end of the program cycle. To read a data memory location, the user must write the address to the EEADR register, clear the EEPGD control bit (EECON1<7>), and then set control bit RD (EECON1<0>). The data is available in the very next cycle, in the EEDATA register; therefore, it can be read in the next instruction (see Example 3-1). EEDATA will hold this value until another read, or until it is written to by the user (during a write operation). The steps to reading the EEPROM data memory are: 1. Write the address to EEADR. Make sure that the address is not larger than the memory size of the device. Clear the EEPGD bit to point to EEPROM data memory. Set the RD bit to start the read operation. Read the data from the EEDATA register.
2. 3. 4.
EXAMPLE 3-1:
BSF BCF MOVF MOVWF BSF BCF BSF BCF MOVF
DATA EEPROM READ
; ; ; ; ; ; ; ; ; ; Bank 2 Data Memory Address to read Bank 3 Point to Data memory EE Read Bank 2 W = EEDATA
STATUS,RP1 STATUS,RP0 DATA_EE_ADDR,W EEADR STATUS,RP0 EECON1,EEPGD EECON1,RD STATUS,RP0 EEDATA,W
EXAMPLE 3-2:
DATA EEPROM WRITE
; ;Wait for write ;to complete ;Bank 2 ;Data Memory ;Address to write ;Data Memory Value ;to write ;Bank 3 ;Point to DATA ;memory ;Enable writes ;Disable INTs. ; ;Write 55h ; ;Write AAh ;Set WR bit to ;begin write ;Enable INTs. ;Disable writes
3.4
Writing to Data EEPROM Memory
To write an EEPROM data location, the user must first write the address to the EEADR register and the data to the EEDATA register. Then the user must follow a specific write sequence to initiate the write for each byte. The write will not initiate if the write sequence is not exactly followed (write 55h to EECON2, write AAh to EECON2, then set WR bit) for each byte. We strongly recommend that interrupts be disabled during this code segment (see Example 3-2). Additionally, the WREN bit in EECON1 must be set to enable write. This mechanism prevents accidental writes to data EEPROM due to errant (unexpected) code execution (i.e., lost programs). The user should keep the WREN bit clear at all times, except when updating EEPROM. The WREN bit is not cleared by hardware After a write sequence has been initiated, clearing the WREN bit will not affect this write cycle. The WR bit will be inhibited from being set unless the WREN bit is set. At the completion of the write cycle, the WR bit is cleared in hardware and the EE Write Complete Interrupt Flag bit (EEIF) is set. The user can either enable this interrupt or poll this bit. EEIF must be cleared by software.
BSF BSF BTFSC GOTO BCF MOVF MOVWF MOVF MOVWF BSF BCF BSF BCF MOVLW MOVWF MOVLW MOVWF BSF BSF BCF
STATUS,RP1 STATUS,RP0 EECON,WR1 $-1 STATUS, RP0 DATA_EE_ADDR,W EEADR DATA_EE_DATA,W EEDATA STATUS,RP0 EECON1,EEPGD EECON1,WREN INTCON,GIE 55h EECON2 AAh EECON2 EECON1,WR INTCON,GIE EECON1,WREN
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Required Sequence
DS39582A-page 33
PIC16F87XA
3.5 Reading FLASH Program Memory
To read a program memory location, the user must write two bytes of the address to the EEADR and EEADRH registers, set the EEPGD control bit (EECON1<7>), and then set control bit RD (EECON1<0>). Once the read control bit is set, the program memory FLASH controller will use the next two instruction cycles to read the data. This causes these two instructions immediately following the "BSF EECON1,RD" instruction to be ignored. The data is available in the very next cycle, in the EEDATA and EEDATH registers; therefore, it can be read as two bytes in the following instructions. EEDATA and EEDATH registers will hold this value until another read or until it is written to by the user (during a write operation).
EXAMPLE 3-3:
BSF BCF MOVLW MOVWF MOVLW MOVWF BSF BSF BSF
Required Sequence
FLASH PROGRAM READ
STATUS, RP1 STATUS, RP0 MS_PROG_EE_ADDR EEADRH LS_PROG_EE_ADDR EEADR STATUS, RP0 EECON1, EEPGD EECON1, RD ; ; ; ; ; ; ; ; ; Bank 2 MS Byte of Program Address to read LS Byte of Program Address to read Bank 3 Point to PROGRAM memory EE Read
; NOP NOP ; BCF MOVF MOVWF MOVF MOVWF STATUS, RP0 EEDATA, W DATAL EEDATH, W DATAH ; ; W = LS Byte of Program EEDATA ; ; W = MS Byte of Program EEDATA ; ; Any instructions here are ignored as program ; memory is read in second cycle after BSF EECON1,RD
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3.6 Writing to FLASH Program Memory
To transfer data from the buffer registers to the program memory, the EEADR and EEADRH must point to the last location in the four-word block (EEADR<1:0> = `11'). Then the following sequence of events must be executed: 1. 2. 3. Set the EEPGD control bit (EECON1<7>) Write 55h, then AAh, to EECON2 (FLASH programming sequence) Set control bit WR (EECON1<1>) to begin the write operation
FLASH program memory may only be written to if the destination address is in a segment of memory that is not write protected, as defined in bits WRT1:WRT0 of the device configuration word (Register 14-1). FLASH program memory must be written in four-word blocks. A block consists of four words with sequential addresses, with a lower boundary defined by an address, where EEADR<1:0> = `00'. At the same time, all block writes to program memory are done as eraseand-write operations. The write operation is edgealigned, and cannot occur across boundaries. To write program data, it must first be loaded into the buffer registers (see Figure 3-1). This is accomplished by first writing the destination address to EEADR and EEADRH, and then writing the data to EEDATA and EEDATH. After the address and data have been set up, then the following sequence of events must be executed: 1. 2. 3. Set the EEPGD control bit (EECON1<7>) Write 55h, then AAh, to EECON2 (FLASH programming sequence) Set the WR control bit (EECON1<1>)
The user must follow the same specific sequence to initiate the write for each word in the program block, writing each program word in sequence (00,01,10,11). When the write is performed on the last word (EEADR<1:0> = `11'), the block of four words are automatically erased, and the contents of the buffer registers are written into the program memory. After the "BSF EECON1,WR" instruction, the processor requires two cycles to set up the erase/write operation. The user must place two NOP instructions after the WR bit is set. Since data is being written to buffer registers, the writing of the first three words of the block appears to occur immediately. The processor will halt internal operations for the typical 4 ms, only during the cycle in which the erase takes place (i.e., the last word of the four-word block). This is not SLEEP mode, as the clocks and peripherals will continue to run. After the write cycle, the processor will resume operation with the third instruction after the EECON1 write instruction. If the sequence is performed to any other location, the action is ignored.
All four buffer register locations MUST be written to with correct data. If only one, two, or three words are being written to in the block of four words, then a read from the program memory location(s) not being written to must be performed. This takes the data from the program location(s) not being written and loads it into the EEDATA and EEDATH registers. Then the sequence of events to transfer data to the buffer registers must be executed.
FIGURE 3-1:
BLOCK WRITES TO FLASH PROGRAM MEMORY
7 5 EEDATH 07 EEDATA 0 Four words of FLASH are erased, then all buffers are transferred to FLASH automatically after this word is written
6
First word of block to be written
8
14
EEADR<1:0> EEADR<1:0> = `01'
14
EEADR<1:0> = `10'
14
EEADR<1:0> = `11'
14
= `00'
Buffer Register
Buffer Register
Buffer Register
Buffer Register
Program Memory
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An example of the complete four-word write sequence is shown in Example 3-4. The initial address is loaded into the EEADRH:EEADR register pair; the four words of data are loaded using indirect addressing.
EXAMPLE 3-4:
; ; ; ; ; ;
WRITING TO FLASH PROGRAM MEMORY
This write routine assumes the following: 1. A valid starting address (the least significant bits = `00')is loaded in ADDRH:ADDRL 2. The 8 bytes of data are loaded, starting at the address in DATADDR 3. ADDRH, ADDRL and DATADDR are all located in shared data memory 0x70 - 0x7f BSF BCF MOVF MOVWF MOVF MOVWF MOVF MOVWF MOVF MOVWF INCF MOVF MOVWF INCF BSF BSF BSF BCF MOVLW MOVWF MOVLW MOVWF BSF NOP NOP BCF BSF BCF INCF MOVF ANDLW XORLW BTFSC GOTO EECON1,WREN INTCON,GIE STATUS,RP0 EEADR,F EEADR,W 0x03 0x03 STATUS,Z LOOP STATUS,RP1 STATUS,RP0 ADDRH,W EEADRH ADDRL,W EEADR DATAADDR,W FSR INDF,W EEDATA FSR,F INDF,W EEDATH FSR,F STATUS,RP0 EECON1,EEPGD EECON1,WREN INTCON,GIE 55h EECON2 AAh EECON2 EECON1,WR ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ;
Bank 2 Load initial address
Load initial data address Load first data byte into lower Next byte Load second data byte into upper
LOOP
Bank 3 Point to program memory Enable writes Disable interrupts (if using) Start of required write sequence: Write 55h Write AAh Set WR bit to begin write Any instructions here are ignored as processor halts to begin write sequence processor will stop here and wait for write complete after write processor continues with 3rd instruction Disable writes Enable interrupts (if using) Bank 2 Increment address Check if lower two bits of address are `00' Indicates when four words have been programmed Exit if more than four words, Continue if less than four words
Required Sequence
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3.7 Protection Against Spurious Write 3.8 Operation During Code Protect
There are conditions when the device should not write to the data EEPROM or FLASH program memory. To protect against spurious writes, various mechanisms have been built-in. On power-up, WREN is cleared. Also, the Power-up Timer (72 ms duration) prevents an EEPROM write. The write initiate sequence and the WREN bit together help prevent an accidental write during brown-out, power glitch, or software malfunction. When the data EEPROM is code protected, the microcontroller can read and write to the EEPROM normally. However, all external access to the EEPROM is disabled. External write access to the program memory is also disabled. When program memory is code protected, the microcontroller can read and write to program memory normally, as well as execute instructions. Writes by the device may be selectively inhibited to regions of the memory, depending on the setting of bits WR1:WR0 of the configuration word (see Section 14.1 for additional information). External access to the memory is also disabled.
TABLE 3-1:
REGISTERS/BITS ASSOCIATED WITH DATA EEPROM AND FLASH PROGRAM MEMORIES
Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on Power-on Reset Value on all other RESETS
Address 10Ch 10Dh 10Eh 10Fh 18Ch 18Dh 0Dh 8Dh
EEDATA EEADR EEDATH EEADRH EECON1 EECON2 PIR2 PIE2
EEPROM/FLASH Data Register Low Byte EEPROM/FLASH Address Register Low Byte -- -- EEPGD -- -- -- EEPROM/FLASH Data Register High Byte -- -- EEPROM/FLASH Address Register High Byte -- WRERR WREN WR RD
xxxx xxxx uuuu uuuu xxxx xxxx uuuu uuuu xxxx xxxx ---0 q000 xxxx xxxx ---- ---x--- x000 ---0 q000 ---- ---- ---- ----
EEPROM Control Register2 (not a physical register) -- -- CMIF CMIE -- -- EEIF EEIE BCLIF BCLIE -- -- -- -- CCP2IF CCP2IE
-0-0 0--0 -0-0 0--0 -0-0 0--0 -0-0 0--0
Legend: x = unknown, u = unchanged, - = unimplemented, read as '0', q = value depends upon condition. Shaded cells are not used by Data EEPROM or FLASH Program Memory.
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NOTES:
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4.0 I/O PORTS
EXAMPLE 4-1:
BCF BCF CLRF
INITIALIZING PORTA
; ; ; ; ; ; ; ; ; ; ; ; ; ; ; Bank0 Initialize PORTA by clearing output data latches Select Bank 1 Configure all pins as digital inputs Value used to initialize data direction Set RA<3:0> as inputs RA<5:4> as outputs TRISA<7:6>are always read as '0'.
Some pins for these I/O ports are multiplexed with an alternate function for the peripheral features on the device. In general, when a peripheral is enabled, that pin may not be used as a general purpose I/O pin. Additional information on I/O ports may be found in the PICmicroTM Mid-Range Reference Manual (DS33023).
STATUS, RP0 STATUS, RP1 PORTA
4.1
PORTA and the TRISA Register
BSF MOVLW MOVWF MOVLW
STATUS, RP0 0x06 ADCON1 0xCF
PORTA is a 6-bit wide, bi-directional port. The corresponding data direction register is TRISA. Setting a TRISA bit (= 1) will make the corresponding PORTA pin an input (i.e., put the corresponding output driver in a Hi-Impedance mode). Clearing a TRISA bit (= 0) will make the corresponding PORTA pin an output (i.e., put the contents of the output latch on the selected pin). Reading the PORTA register reads the status of the pins, whereas writing to it will write to the port latch. All write operations are read-modify-write operations. Therefore, a write to a port implies that the port pins are read, the value is modified and then written to the port data latch. Pin RA4 is multiplexed with the Timer0 module clock input to become the RA4/T0CKI pin. The RA4/T0CKI pin is a Schmitt Trigger input and an open drain output. All other PORTA pins have TTL input levels and full CMOS output drivers. Other PORTA pins are multiplexed with analog inputs and the analog VREF input for both the A/D converters and the comparators. The operation of each pin is selected by clearing/setting the appropriate control bits in the ADCON1 and/or CMCON registers. Note: On a Power-on Reset, these pins are configured as analog inputs and read as '0'. The comparators are in the Off (digital) state.
MOVWF
TRISA
FIGURE 4-1:
Data Bus Data Latch D Q
BLOCK DIAGRAM OF RA3:RA0 PINS
WR PORTA
VDD CK Q P I/O pin(1)
TRIS Latch D WR TRISA Q N
CK
Q
VSS Analog Input Mode
RD TRISA
TTL Input Buffer Q D
The TRISA register controls the direction of the port pins, even when they are being used as analog inputs. The user must ensure the bits in the TRISA register are maintained set when using them as analog inputs.
EN
RD PORTA
To A/D Converter or Comparator Note 1: I/O pins have protection diodes to VDD and VSS.
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FIGURE 4-2: BLOCK DIAGRAM OF RA4/T0CKI PIN
CMCON<2:0> = `x01' or `011' C1OUT Data Latch Data Bus WR PORTA D Q Q 1 N I/O pin(1)
CK
0
TRIS Latch D WR TRISA Q Q
VSS
CK
Schmitt Trigger Input Buffer
RD TRISA Q D EN EN RD PORTA TMR0 Clock Input
Note 1: I/O pin has protection diodes to VSS only.
FIGURE 4-3:
BLOCK DIAGRAM OF RA5 PIN
CMCON<2:0> = `011' or `101' C2OUT Data Latch Data Bus WR PORTA D Q Q 1
VDD P
CK
0 N I/O pin(1)
TRIS Latch D WR TRISA Q Q
CK
VSS
Schmitt Trigger Input Buffer
RD TRISA Q D EN EN RD PORTA A/D Converter or SS Input
Note 1: I/O pin has protection diodes to VDD and VSS.
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TABLE 4-1:
Name RA0/AN0 RA1/AN1 RA2/AN2/VREF-/CVREF RA3/AN3/VREF+ RA4/T0CKI/C1OUT RA5/SS/AN4/C2OUT
PORTA FUNCTIONS
Bit# bit0 bit1 bit2 bit3 bit4 bit5 Buffer TTL TTL TTL TTL ST TTL Input/output or analog input. Input/output or analog input. Input/output or analog input or VREF- or CVREF. Input/output or analog input or VREF+. Input/output or external clock input for Timer0 or comparator output. Output is open drain type. Input/output or slave select input for synchronous serial port or analog input or comparator output. Function
Legend: TTL = TTL input, ST = Schmitt Trigger input
TABLE 4-2:
Address 05h 85h 9Ch 9Dh 9Fh Name PORTA TRISA CMCON
SUMMARY OF REGISTERS ASSOCIATED WITH PORTA
Bit 7 -- -- C2OUT ADFM Bit 6 -- -- C1OUT ADCS2 Bit 5 RA5 C2INV CVRR -- Bit 4 RA4 C1INV -- -- Bit 3 RA3 CIS CVR3 PCFG3 Bit 2 RA2 CM2 CVR2 PCFG2 Bit 1 RA1 CM1 CVR1 PCFG1 Bit 0 RA0 CM0 CVR0 PCFG0 Value on: POR, BOR
--0x 0000 --11 1111 0000 0111 000- 0000 --0- 0000
Value on all other RESETS
--0u 0000 --11 1111 0000 0111 000- 0000 --0- 0000
PORTA Data Direction Register
CVRCON ADCON1
CVREN CVROE
Legend: x = unknown, u = unchanged, - = unimplemented locations read as '0'. Shaded cells are not used by PORTA.
Note:
When using the SSP module in SPI Slave mode and SS enabled, the A/D converter must be set to one of the following modes, where PCFG3:PCFG0 = 0100, 0101, 011x, 1101, 1110, 1111.
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4.2 PORTB and the TRISB Register
PORTB is an 8-bit wide, bi-directional port. The corresponding data direction register is TRISB. Setting a TRISB bit (= 1) will make the corresponding PORTB pin an input (i.e., put the corresponding output driver in a Hi-Impedance mode). Clearing a TRISB bit (= 0) will make the corresponding PORTB pin an output (i.e., put the contents of the output latch on the selected pin). Three pins of PORTB are multiplexed with the InCircuit Debugger and Low Voltage Programming function: RB3/PGM, RB6/PGC and RB7/PGD. The alternate functions of these pins are described in the Special Features Section. Each of the PORTB pins has a weak internal pull-up. A single control bit can turn on all the pull-ups. This is performed by clearing bit RBPU (OPTION_REG<7>). The weak pull-up is automatically turned off when the port pin is configured as an output. The pull-ups are disabled on a Power-on Reset. This interrupt can wake the device from SLEEP. The user, in the Interrupt Service Routine, can clear the interrupt in the following manner: a) b) Any read or write of PORTB. This will end the mismatch condition. Clear flag bit RBIF.
A mismatch condition will continue to set flag bit RBIF. Reading PORTB will end the mismatch condition and allow flag bit RBIF to be cleared. The interrupt-on-change feature is recommended for wake-up on key depression operation and operations where PORTB is only used for the interrupt-on-change feature. Polling of PORTB is not recommended while using the interrupt-on-change feature. This interrupt-on-mismatch feature, together with software configureable pull-ups on these four pins, allow easy interface to a keypad and make it possible for wake-up on key depression. Refer to the Embedded Control Handbook, "Implementing Wake-up on Key Strokes" (AN552). RB0/INT is an external interrupt input pin and is configured using the INTEDG bit (OPTION_REG<6>). RB0/INT is discussed in detail in Section 14.11.1.
FIGURE 4-4:
BLOCK DIAGRAM OF RB3:RB0 PINS
VDD Weak P Pull-up Data Latch D CK TRIS Latch D Q TTL Input Buffer Q I/O pin(1)
RBPU(2)
Data Bus WR Port
FIGURE 4-5:
BLOCK DIAGRAM OF RB7:RB4 PINS
VDD Weak P Pull-up Data Latch D Q CK TRIS Latch D Q I/O pin(1)
RBPU(2)
Data Bus WR Port
WR TRIS
CK
RD TRIS Q RD Port EN RB0/INT RB3/PGM Schmitt Trigger Buffer RD Port RD TRIS D WR TRIS
CK
TTL Input Buffer
ST Buffer
Latch Q D EN Q1
RD Port Set RBIF
Note 1: I/O pins have diode protection to VDD and VSS. 2: To enable weak pull-ups, set the appropriate TRIS bit(s) and clear the RBPU bit (OPTION_REG<7>).
Q
D RD Port EN Q3
Four of the PORTB pins, RB7:RB4, have an interrupton-change feature. Only pins configured as inputs can cause this interrupt to occur (i.e., any RB7:RB4 pin configured as an output is excluded from the interrupton-change comparison). The input pins (of RB7:RB4) are compared with the old value latched on the last read of PORTB. The "mismatch" outputs of RB7:RB4 are OR'ed together to generate the RB Port Change Interrupt with flag bit RBIF (INTCON<0>).
From other RB7:RB4 pins RB7:RB6 In Serial Programming Mode
Note 1: I/O pins have diode protection to VDD and VSS. 2: To enable weak pull-ups, set the appropriate TRIS bit(s) and clear the RBPU bit (OPTION_REG<7>).
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TABLE 4-3:
Name RB0/INT RB1 RB2 RB3/PGM RB4 RB5 RB6/PGC RB7/PGD
(3)
PORTB FUNCTIONS
Bit# bit0 bit1 bit2 bit3 bit4 bit5 bit6 bit7 Buffer TTL/ST(1) TTL TTL TTL TTL TTL TTL/ST(2) TTL/ST(2) Function Input/output pin or external interrupt input. Internal software programmable weak pull-up. Input/output pin. Internal software programmable weak pull-up. Input/output pin. Internal software programmable weak pull-up. Input/output pin or programming pin in LVP mode. Internal software programmable weak pull-up. Input/output pin (with interrupt-on-change). Internal software programmable weak pull-up. Input/output pin (with interrupt-on-change). Internal software programmable weak pull-up. Input/output pin (with interrupt-on-change) or In-Circuit Debugger pin. Internal software programmable weak pull-up. Serial programming clock. Input/output pin (with interrupt-on-change) or In-Circuit Debugger pin. Internal software programmable weak pull-up. Serial programming data.
Legend: TTL = TTL input, ST = Schmitt Trigger input Note 1: This buffer is a Schmitt Trigger input when configured as the external interrupt. 2: This buffer is a Schmitt Trigger input when used in Serial Programming mode or In-Circuit Debugger. 3: Low Voltage ICSP Programming (LVP) is enabled by default, which disables the RB3 I/O function. LVP must be disabled to enable RB3 as an I/O pin and allow maximum compatibility to the other 28-pin and 40-pin mid-range devices.
TABLE 4-4:
Address 06h, 106h 86h, 186h 81h, 181h
SUMMARY OF REGISTERS ASSOCIATED WITH PORTB
Name Bit 7 RB7 Bit 6 RB6 INTEDG Bit 5 RB5 Bit 4 RB4 Bit 3 Bit 2 Bit 1 Bit 0 RB3 PSA RB2 PS2 RB1 PS1 Value on: POR, BOR Value on all other RESETS
PORTB TRISB
RB0 xxxx xxxx uuuu uuuu
1111 1111 1111 1111
PORTB Data Direction Register T0CS T0SE PS0
OPTION_REG RBPU
1111 1111 1111 1111
Legend: x = unknown, u = unchanged. Shaded cells are not used by PORTB.
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4.3 PORTC and the TRISC Register
FIGURE 4-7:
PORTC is an 8-bit wide, bi-directional port. The corresponding data direction register is TRISC. Setting a TRISC bit (= 1) will make the corresponding PORTC pin an input (i.e., put the corresponding output driver in a Hi-Impedance mode). Clearing a TRISC bit (= 0) will make the corresponding PORTC pin an output (i.e., put the contents of the output latch on the selected pin). PORTC is multiplexed with several peripheral functions (Table 4-5). PORTC pins have Schmitt Trigger input buffers. When the I2C module is enabled, the PORTC<4:3> pins can be configured with normal I2C levels, or with SMBus levels, by using the CKE bit (SSPSTAT<6>). When enabling peripheral functions, care should be taken in defining TRIS bits for each PORTC pin. Some peripherals override the TRIS bit to make a pin an output, while other peripherals override the TRIS bit to make a pin an input. Since the TRIS bit override is in effect while the peripheral is enabled, read-modifywrite instructions (BSF, BCF, XORWF) with TRISC as the destination, should be avoided. The user should refer to the corresponding peripheral section for the correct TRIS bit settings.
PORTC BLOCK DIAGRAM (PERIPHERAL OUTPUT OVERRIDE) RC<4:3>
Port/Peripheral Select(2) Peripheral Data Out Data Bus WR Port D CK Q Q 1 0
VDD P I/O pin(1)
Data Latch WR TRIS D CK Q Q N Vss Schmitt Trigger Q D EN 0 Schmitt Trigger with SMBus Levels
TRIS Latch RD TRIS Peripheral OE(3) RD Port SSPl Input 1 CKE SSPSTAT<6> Note 1: I/O pins have diode protection to VDD and VSS. 2: Port/Peripheral Select signal selects between port data and peripheral output. 3: Peripheral OE (output enable) is only activated if Peripheral Select is active.
FIGURE 4-6:
PORTC BLOCK DIAGRAM (PERIPHERAL OUTPUT OVERRIDE) RC<2:0>, RC<7:5>
Port/Peripheral Select(2) Peripheral Data Out Data Bus WR Port D CK Q Q 1 0 VDD P I/O pin(1)
Data Latch WR TRIS D CK Q Q N VSS Schmitt Trigger Q D EN
TRIS Latch RD TRIS Peripheral OE(3) RD Port Peripheral Input Note 1: I/O pins have diode protection to VDD and VSS. 2: Port/Peripheral Select signal selects between port data and peripheral output. 3: Peripheral OE (output enable) is only activated if Peripheral Select is active.
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TABLE 4-5:
Name RC0/T1OSO/T1CKI RC1/T1OSI/CCP2 RC2/CCP1 RC3/SCK/SCL RC4/SDI/SDA RC5/SDO RC6/TX/CK RC7/RX/DT
PORTC FUNCTIONS
Bit# bit0 bit1 bit2 bit3 bit4 bit5 bit6 bit7 Buffer Type ST ST ST ST ST ST ST ST Function Input/output port pin or Timer1 oscillator output/Timer1 clock input. Input/output port pin or Timer1 oscillator input or Capture2 input/ Compare2 output/PWM2 output. Input/output port pin or Capture1 input/Compare1 output/ PWM1 output. RC3 can also be the synchronous serial clock for both SPI and I2C modes. RC4 can also be the SPI Data In (SPI mode) or Data I/O (I2C mode). Input/output port pin or Synchronous Serial Port data output. Input/output port pin or USART Asynchronous Transmit or Synchronous Clock. Input/output port pin or USART Asynchronous Receive or Synchronous Data.
Legend: ST = Schmitt Trigger input
TABLE 4-6:
Address 07h 87h
SUMMARY OF REGISTERS ASSOCIATED WITH PORTC
Bit 7 RC7 Bit 6 RC6 Bit 5 RC5 Bit 4 RC4 Bit 3 RC3 Bit 2 RC2 Bit 1 RC1 Bit 0 RC0 Value on: POR, BOR
xxxx xxxx 1111 1111
Name PORTC TRISC
Value on all other RESETS
uuuu uuuu 1111 1111
PORTC Data Direction Register
Legend: x = unknown, u = unchanged
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4.4
Note:
PORTD and TRISD Registers
PORTD and TRISD are not implemented on the 28-pin devices.
FIGURE 4-8:
Data Bus WR Port
PORTD BLOCK DIAGRAM (IN I/O PORT MODE)
I/O pin(1)
PORTD is an 8-bit port with Schmitt Trigger input buffers. Each pin is individually configureable as an input or output. PORTD can be configured as an 8-bit wide microprocessor port (parallel slave port) by setting control bit PSPMODE (TRISE<4>). In this mode, the input buffers are TTL.
Data Latch D Q
CK TRIS Latch D Q
WR TRIS
CK
Schmitt Trigger Input Buffer
RD TRIS
Q
D EN EN
RD Port
Note 1: I/O pins have protection diodes to VDD and VSS.
TABLE 4-7:
Name RD0/PSP0 RD1/PSP1 RD2/PSP2 RD3/PSP3 RD4/PSP4 RD5/PSP5 RD6/PSP6 RD7/PSP7
PORTD FUNCTIONS
Bit# bit0 bit1 bit2 bit3 bit4 bit5 bit6 bit7 Buffer Type ST/TTL(1) ST/TTL(1) ST/TTL
(1)
Function Input/output port pin or parallel slave port bit0. Input/output port pin or parallel slave port bit1. Input/output port pin or parallel slave port bit2. Input/output port pin or parallel slave port bit3. Input/output port pin or parallel slave port bit4. Input/output port pin or parallel slave port bit5. Input/output port pin or parallel slave port bit6. Input/output port pin or parallel slave port bit7.
ST/TTL(1) ST/TTL(1) ST/TTL(1) ST/TTL
(1)
ST/TTL(1)
Legend: ST = Schmitt Trigger input, TTL = TTL input Note 1: Input buffers are Schmitt Triggers when in I/O mode and TTL buffers when in Parallel Slave Port mode.
TABLE 4-8:
Address 08h 88h 89h
SUMMARY OF REGISTERS ASSOCIATED WITH PORTD
Bit 7 RD7 IBF Bit 6 RD6 Bit 5 RD5 Bit 4 RD4 Bit 3 RD3 -- Bit 2 RD2 Bit 1 RD1 Bit 0 RD0 Value on: POR, BOR
xxxx xxxx 1111 1111
Name PORTD TRISD TRISE
Value on all other RESETS
uuuu uuuu 1111 1111 0000 -111
PORTD Data Direction Register OBF IBOV PSPMODE PORTE Data Direction Bits
0000 -111
Legend: x = unknown, u = unchanged, - = unimplemented, read as '0'. Shaded cells are not used by PORTD.
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4.5
Note:
PORTE and TRISE Register
PORTE and TRISE are not implemented on the 28-pin devices.
FIGURE 4-9:
PORTE BLOCK DIAGRAM (IN I/O PORT MODE)
I/O pin(1)
PORTE has three pins (RE0/RD/AN5, RE1/WR/AN6, and RE2/CS/AN7), which are individually configurable as inputs or outputs. These pins have Schmitt Trigger input buffers. The PORTE pins become the I/O control inputs for the microprocessor port when bit PSPMODE (TRISE<4>) is set. In this mode, the user must make certain that the TRISE<2:0> bits are set, and that the pins are configured as digital inputs. Also ensure that ADCON1 is configured for digital I/O. In this mode, the input buffers are TTL. Register 4-1 shows the TRISE register, which also controls the parallel slave port operation. PORTE pins are multiplexed with analog inputs. When selected for analog input, these pins will read as '0's. TRISE controls the direction of the RE pins, even when they are being used as analog inputs. The user must make sure to keep the pins configured as inputs when using them as analog inputs. Note: On a Power-on Reset, these pins are configured as analog inputs, and read as `0'.
Data Bus WR Port
Data Latch D Q
CK TRIS Latch D Q Schmitt Trigger Input Buffer
WR TRIS
CK
RD TRIS
Q
D EN EN
RD Port
Note 1: I/O pins have protection diodes to VDD and VSS.
TABLE 4-9:
Name
PORTE FUNCTIONS
Bit# Buffer Type Function I/O port pin or read control input in Parallel Slave Port mode or analog input: RD 1 = Idle 0 = Read operation. Contents of PORTD register are output to PORTD I/O pins (if chip selected). I/O port pin or write control input in Parallel Slave Port mode or analog input: WR 1 = Idle 0 = Write operation. Value of PORTD I/O pins is latched into PORTD register (if chip selected). I/O port pin or chip select control input in Parallel Slave Port mode or analog input: CS 1 = Device is not selected 0 = Device is selected
RE0/RD/AN5
bit0
ST/TTL(1)
RE1/WR/AN6
bit1
ST/TTL(1)
RE2/CS/AN7
bit2
ST/TTL(1)
Legend: ST = Schmitt Trigger input, TTL = TTL input Note 1: Input buffers are Schmitt Triggers when in I/O mode and TTL buffers when in Parallel Slave Port mode.
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TABLE 4-10:
Address 09h 89h 9Fh Name PORTE TRISE ADCON1
SUMMARY OF REGISTERS ASSOCIATED WITH PORTE
Bit 7 -- IBF ADFM Bit 6 -- OBF ADCS2 Bit 5 -- IBOV -- Bit 4 -- PSPMODE -- Bit 3 -- -- PCFG3 Bit 2 RE2 PCFG2 Bit 1 RE1 PCFG1 Bit 0 RE0 PCFG0 Value on: POR, BOR Value on all other RESETS
---- -xxx ---- -uuu 0000 -111 0000 -111 --0- 0000 --0- 0000
PORTE Data Direction Bits
Legend: x = unknown, u = unchanged, - = unimplemented, read as '0'. Shaded cells are not used by PORTE.
REGISTER 4-1:
TRISE REGISTER (ADDRESS 89h)
R-0 IBF bit 7 Parallel Slave Port Status/Control Bits: R-0 OBF R/W-0 IBOV R/W-0 PSPMODE U-0 -- R/W-1 Bit2 R/W-1 Bit1 R/W-1 Bit0 bit 0
bit 7
IBF: Input Buffer Full Status bit 1 = A word has been received and is waiting to be read by the CPU 0 = No word has been received OBF: Output Buffer Full Status bit 1 = The output buffer still holds a previously written word 0 = The output buffer has been read IBOV: Input Buffer Overflow Detect bit (in Microprocessor mode) 1 = A write occurred when a previously input word has not been read (must be cleared in software) 0 = No overflow occurred PSPMODE: Parallel Slave Port Mode Select bit 1 = PORTD functions in Parallel Slave Port mode 0 = PORTD functions in general purpose I/O mode Unimplemented: Read as '0' PORTE Data Direction Bits: Bit2: Direction Control bit for pin RE2/CS/AN7 1 = Input 0 = Output Bit1: Direction Control bit for pin RE1/WR/AN6 1 = Input 0 = Output Bit0: Direction Control bit for pin RE0/RD/AN5 1 = Input 0 = Output Legend: R = Readable bit - n = Value at POR W = Writable bit '1' = Bit is set U = Unimplemented bit, read as `0' '0' = Bit is cleared x = Bit is unknown
bit 6
bit 5
bit 4
bit 3 bit 2
bit 1
bit 0
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4.6 Parallel Slave Port
FIGURE 4-10:
The Parallel Slave Port (PSP) is not implemented on the PIC16F873A or PIC16F876A. PORTD operates as an 8-bit wide Parallel Slave Port or microprocessor port, when control bit PSPMODE (TRISE<4>) is set. In Slave mode, it is asynchronously readable and writable by the external world through RD control input pin, RE0/RD and WR control input pin, RE1/WR. The PSP can directly interface to an 8-bit microprocessor data bus. The external microprocessor can read or write the PORTD latch as an 8-bit latch. Setting bit PSPMODE enables port pin RE0/RD to be the RD input, RE1/WR to be the WR input and RE2/CS to be the CS (chip select) input. For this functionality, the corresponding data direction bits of the TRISE register (TRISE<2:0>) must be configured as inputs (set). The A/D port configuration bits, PCFG3:PCFG0 (ADCON1<3:0>), must be set to configure pins RE2:RE0 as digital I/O. There are actually two 8-bit latches: one for data output, and one for data input. The user writes 8-bit data to the PORTD data latch and reads data from the port pin latch (note that they have the same address). In this mode, the TRISD register is ignored, since the external device is controlling the direction of data flow. A write to the PSP occurs when both the CS and WR lines are first detected low. When either the CS or WR lines become high (level triggered), the Input Buffer Full (IBF) status flag bit (TRISE<7>) is set on the Q4 clock cycle, following the next Q2 cycle, to signal the write is complete (Figure 4-11). The interrupt flag bit PSPIF (PIR1<7>) is also set on the same Q4 clock cycle. IBF can only be cleared by reading the PORTD input latch. The Input Buffer Overflow (IBOV) status flag bit (TRISE<5>) is set if a second write to the PSP is attempted when the previous byte has not been read out of the buffer. A read from the PSP occurs when both the CS and RD lines are first detected low. The Output Buffer Full (OBF) status flag bit (TRISE<6>) is cleared immediately (Figure 4-12), indicating that the PORTD latch is waiting to be read by the external bus. When either the CS or RD pin becomes high (level triggered), the interrupt flag bit PSPIF is set on the Q4 clock cycle, following the next Q2 cycle, indicating that the read is complete. OBF remains low until data is written to PORTD by the user firmware. When not in PSP mode, the IBF and OBF bits are held clear. However, if flag bit IBOV was previously set, it must be cleared in firmware. An interrupt is generated and latched into flag bit PSPIF when a read or write operation is completed. PSPIF must be cleared by the user in firmware and the interrupt can be disabled by clearing the interrupt enable bit PSPIE (PIE1<7>).
PORTD AND PORTE BLOCK DIAGRAM (PARALLEL SLAVE PORT)
Data Bus D WR Port Q RDx pin TTL Q RD Port One bit of PORTD Set Interrupt Flag PSPIF(PIR1<7>) D EN EN
CK
Read
TTL
RD
Chip Select TTL Write TTL Note 1: I/O pins have protection diodes to VDD and VSS.
CS
WR
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FIGURE 4-11: PARALLEL SLAVE PORT WRITE WAVEFORMS
Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4
CS WR RD PORTD<7:0> IBF OBF PSPIF
FIGURE 4-12:
PARALLEL SLAVE PORT READ WAVEFORMS
Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4
CS WR RD PORTD<7:0> IBF OBF PSPIF
TABLE 4-11:
Address 08h 09h 89h 0Ch 8Ch 9Fh Name PORTD PORTE TRISE PIR1 PIE1
REGISTERS ASSOCIATED WITH PARALLEL SLAVE PORT
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on: POR, BOR Value on all other RESETS
Port Data Latch when written; Port pins when read -- IBF PSPIF(1) PSPIE(1) ADFM -- OBF ADIF ADIE ADCS2 -- IBOV RCIF RCIE -- -- PSPMODE TXIF TXIE -- -- -- SSPIF SSPIE PCFG3 RE2 CCP1IF PCFG2 RE1 TMR2IF PCFG1 RE0 PORTE Data Direction Bits
xxxx xxxx uuuu uuuu ---- -xxx ---- -uuu 0000 -111 0000 -111
TMR1IF 0000 0000 0000 0000 PCFG0
--0- 0000 --0- 0000
CCP1IE TMR2IE TMR1IE 0000 0000 0000 0000
ADCON1
Legend: x = unknown, u = unchanged, - = unimplemented, read as '0'. Shaded cells are not used by the Parallel Slave Port. Note 1: Bits PSPIE and PSPIF are reserved on the PIC16F873A/876A; always maintain these bits clear.
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5.0 TIMER0 MODULE
The Timer0 module timer/counter has the following features: * * * * * * 8-bit timer/counter Readable and writable 8-bit software programmable prescaler Internal or external clock select Interrupt on overflow from FFh to 00h Edge select for external clock Counter mode is selected by setting bit T0CS (OPTION_REG<5>). In Counter mode, Timer0 will increment either on every rising, or falling edge of pin RA4/T0CKI. The incrementing edge is determined by the Timer0 Source Edge Select bit, T0SE (OPTION_REG<4>). Clearing bit T0SE selects the rising edge. Restrictions on the external clock input are discussed in detail in Section 5.2. The prescaler is mutually exclusively shared between the Timer0 module and the Watchdog Timer. The prescaler is not readable or writable. Section 5.3 details the operation of the prescaler.
Figure 5-1 is a block diagram of the Timer0 module and the prescaler shared with the WDT. Additional information on the Timer0 module is available in the PICmicroTM Mid-Range MCU Family Reference Manual (DS33023). Timer mode is selected by clearing bit T0CS (OPTION_REG<5>). In Timer mode, the Timer0 module will increment every instruction cycle (without prescaler). If the TMR0 register is written, the increment is inhibited for the following two instruction cycles. The user can work around this by writing an adjusted value to the TMR0 register.
5.1
Timer0 Interrupt
The TMR0 interrupt is generated when the TMR0 register overflows from FFh to 00h. This overflow sets bit TMR0IF (INTCON<2>). The interrupt can be masked by clearing bit TMR0IE (INTCON<5>). Bit TMR0IF must be cleared in software by the Timer0 module Interrupt Service Routine before re-enabling this interrupt. The TMR0 interrupt cannot awaken the processor from SLEEP, since the timer is shut-off during SLEEP.
FIGURE 5-1:
BLOCK DIAGRAM OF THE TIMER0/WDT PRESCALER
Data Bus 8 1 0 M U X SYNC 2 Cycles TMR0 Reg
CLKOUT (= FOSC/4)
0 RA4/T0CKI pin 1 T0SE
M U X
T0CS
PSA PRESCALER
Set Flag Bit TMR0IF on Overflow
0 M U X
8-bit Prescaler 8 8 - to - 1MUX PS2:PS0
Watchdog Timer
1
PSA 0 MUX 1 PSA
WDT Enable bit
WDT Time-out Note: T0CS, T0SE, PSA, PS2:PS0 are (OPTION_REG<5:0>).
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5.2 Using Timer0 with an External Clock
Timer0 module means that there is no prescaler for the Watchdog Timer, and vice-versa. This prescaler is not readable or writable (see Figure 5-1). The PSA and PS2:PS0 bits (OPTION_REG<3:0>) determine the prescaler assignment and prescale ratio. When assigned to the Timer0 module, all instructions writing to the TMR0 register (e.g. CLRF 1, MOVWF 1, BSF 1,x....etc.) will clear the prescaler. When assigned to WDT, a CLRWDT instruction will clear the prescaler along with the Watchdog Timer. The prescaler is not readable or writable. Note: Writing to TMR0, when the prescaler is assigned to Timer0, will clear the prescaler count, but will not change the prescaler assignment.
When no prescaler is used, the external clock input is the same as the prescaler output. The synchronization of T0CKI with the internal phase clocks is accomplished by sampling the prescaler output on the Q2 and Q4 cycles of the internal phase clocks. Therefore, it is necessary for T0CKI to be high for at least 2Tosc (and a small RC delay of 20 ns) and low for at least 2Tosc (and a small RC delay of 20 ns). Refer to the electrical specification of the desired device.
5.3
Prescaler
There is only one prescaler available, which is mutually exclusively shared between the Timer0 module and the Watchdog Timer. A prescaler assignment for the
REGISTER 5-1:
OPTION_REG REGISTER
R/W-1 RBPU bit 7 R/W-1 INTEDG R/W-1 T0CS R/W-1 T0SE R/W-1 PSA R/W-1 PS2 R/W-1 PS1 R/W-1 PS0 bit 0
bit 7 bit 6 bit 5
RBPU INTEDG T0CS: TMR0 Clock Source Select bit 1 = Transition on T0CKI pin 0 = Internal instruction cycle clock (CLKOUT) T0SE: TMR0 Source Edge Select bit 1 = Increment on high-to-low transition on T0CKI pin 0 = Increment on low-to-high transition on T0CKI pin PSA: Prescaler Assignment bit 1 = Prescaler is assigned to the WDT 0 = Prescaler is assigned to the Timer0 module PS2:PS0: Prescaler Rate Select bits Bit Value TMR0 Rate WDT Rate 000 001 010 011 100 101 110 111 1:2 1:4 1:8 1 : 16 1 : 32 1 : 64 1 : 128 1 : 256 1:1 1:2 1:4 1:8 1 : 16 1 : 32 1 : 64 1 : 128
bit 4
bit 3
bit 2-0
Legend: R = Readable bit - n = Value at POR Note: W = Writable bit '1' = Bit is set U = Unimplemented bit, read as `0' '0' = Bit is cleared x = Bit is unknown
To avoid an unintended device RESET, the instruction sequence shown in the PICmicroTM Mid-Range MCU Family Reference Manual (DS33023) must be executed when changing the prescaler assignment from Timer0 to the WDT. This sequence must be followed even if the WDT is disabled.
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TABLE 5-1:
Address 01h,101h
REGISTERS ASSOCIATED WITH TIMER0
Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on: POR, BOR Value on all other RESETS
TMR0
Timer0 Module Register GIE PEIE TMR0IE INTE RBIE TMR0IF INTF T0CS T0SE PSA PS2 PS1
xxxx xxxx uuuu uuuu
0Bh,8Bh, INTCON 10Bh,18Bh 81h,181h
RBIF 0000 000x 0000 000u PS0 1111 1111 1111 1111
OPTION_REG RBPU INTEDG
Legend: x = unknown, u = unchanged, - = unimplemented locations read as '0'. Shaded cells are not used by Timer0.
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NOTES:
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6.0 TIMER1 MODULE
The Timer1 module is a 16-bit timer/counter consisting of two 8-bit registers (TMR1H and TMR1L), which are readable and writable. The TMR1 Register pair (TMR1H:TMR1L) increments from 0000h to FFFFh and rolls over to 0000h. The TMR1 Interrupt, if enabled, is generated on overflow, which is latched in interrupt flag bit, TMR1IF (PIR1<0>). This interrupt can be enabled/disabled by setting/clearing TMR1 interrupt enable bit, TMR1IE (PIE1<0>). Timer1 can operate in one of two modes: * As a Timer * As a Counter The operating mode is determined by the clock select bit, TMR1CS (T1CON<1>). In Timer mode, Timer1 increments every instruction cycle. In Counter mode, it increments on every rising edge of the external clock input. Timer1 can be enabled/disabled by setting/clearing control bit, TMR1ON (T1CON<0>). Timer1 also has an internal "RESET input". This RESET can be generated by either of the two CCP modules (Section 8.0). Register 6-1 shows the Timer1 control register. When the Timer1 oscillator is enabled (T1OSCEN is set), the RC1/T1OSI/CCP2 and RC0/T1OSO/T1CKI pins become inputs. That is, the TRISC<1:0> value is ignored, and these pins read as `0'. Additional information on timer modules is available in the PICmicroTM Mid-Range MCU Family Reference Manual (DS33023).
REGISTER 6-1:
T1CON: TIMER1 CONTROL REGISTER (ADDRESS 10h)
U-0 -- bit 7 U-0 -- R/W-0 R/W-0 R/W-0 T1OSCEN R/W-0 R/W-0 R/W-0 bit 0
T1CKPS1 T1CKPS0
T1SYNC TMR1CS TMR1ON
bit 7-6 bit 5-4
Unimplemented: Read as '0' T1CKPS1:T1CKPS0: Timer1 Input Clock Prescale Select bits 11 = 1:8 Prescale value 10 = 1:4 Prescale value 01 = 1:2 Prescale value 00 = 1:1 Prescale value T1OSCEN: Timer1 Oscillator Enable Control bit 1 = Oscillator is enabled 0 = Oscillator is shut-off (the oscillator inverter is turned off to eliminate power drain) T1SYNC: Timer1 External Clock Input Synchronization Control bit When TMR1CS = 1: 1 = Do not synchronize external clock input 0 = Synchronize external clock input When TMR1CS = 0: This bit is ignored. Timer1 uses the internal clock when TMR1CS = 0. TMR1CS: Timer1 Clock Source Select bit 1 = External clock from pin RC0/T1OSO/T1CKI (on the rising edge) 0 = Internal clock (FOSC/4) TMR1ON: Timer1 On bit 1 = Enables Timer1 0 = Stops Timer1 Legend: R = Readable bit - n = Value at POR W = Writable bit '1' = Bit is set U = Unimplemented bit, read as `0' '0' = Bit is cleared x = Bit is unknown
bit 3
bit 2
bit 1
bit 0
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6.1 Timer1 Operation in Timer Mode 6.2 Timer1 Counter Operation
Timer mode is selected by clearing the TMR1CS (T1CON<1>) bit. In this mode, the input clock to the timer is FOSC/4. The synchronize control bit, T1SYNC (T1CON<2>), has no effect, since the internal clock is always in sync. Timer1 may operate in either a Synchronous, or an Asynchronous mode, depending on the setting of the TMR1CS bit. When Timer1 is being incremented via an external source, increments occur on a rising edge. After Timer1 is enabled in Counter mode, the module must first have a falling edge before the counter begins to increment.
FIGURE 6-1:
T1CKI (Default High)
TIMER1 INCREMENTING EDGE
T1CKI (Default Low)
Note: Arrows indicate counter increments.
6.3
Timer1 Operation in Synchronized Counter Mode
Counter mode is selected by setting bit TMR1CS. In this mode, the timer increments on every rising edge of clock input on pin RC1/T1OSI/CCP2 when bit T1OSCEN is set, or on pin RC0/T1OSO/T1CKI when bit T1OSCEN is cleared.
If T1SYNC is cleared, then the external clock input is synchronized with internal phase clocks. The synchronization is done after the prescaler stage. The prescaler stage is an asynchronous ripple counter. In this configuration during SLEEP mode, Timer1 will not increment even if the external clock is present, since the synchronization circuit is shut-off. The prescaler, however, will continue to increment.
FIGURE 6-2:
TIMER1 BLOCK DIAGRAM
Set Flag bit TMR1IF on Overflow TMR1H
TMR1 TMR1L
0 1 TMR1ON On/Off T1SYNC
Synchronized Clock Input
T1OSC RC0/T1OSO/T1CKI T1OSCEN FOSC/4 Enable Internal Oscillator(1) Clock 1 Prescaler 1, 2, 4, 8 0 2 T1CKPS1:T1CKPS0 TMR1CS Note 1: When the T1OSCEN bit is cleared, the inverter is turned off. This eliminates power drain. Q Clock Synchronize det
RC1/T1OSI/CCP2(2)
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6.4 Timer1 Operation in Asynchronous Counter Mode
TABLE 6-1:
Osc Type LP
CAPACITOR SELECTION FOR THE TIMER1 OSCILLATOR
Freq. C1 C2
If control bit T1SYNC (T1CON<2>) is set, the external clock input is not synchronized. The timer continues to increment asynchronous to the internal phase clocks. The timer will continue to run during SLEEP and can generate an interrupt-on-overflow, which will wake-up the processor. However, special precautions in software are needed to read/write the timer (Section 6.4.1). In Asynchronous Counter mode, Timer1 cannot be used as a time-base for capture or compare operations.
32 kHz 33 pF 33 pF 100 kHz 15 pF 15 pF 200 kHz 15 pF 15 pF These values are for design guidance only. Crystals Tested: 32.768 kHz Epson C-001R32.768K-A 20 PPM 100 kHz Epson C-2 100.00 KC-P 20 PPM 200 kHz STD XTL 200.000 kHz 20 PPM Note 1: Higher capacitance increases the stability of oscillator, but also increases the start-up time. 2: Since each resonator/crystal has its own characteristics, the user should consult the resonator/crystal manufacturer for appropriate values of external components.
6.4.1
READING AND WRITING TIMER1 IN ASYNCHRONOUS COUNTER MODE
Reading TMR1H or TMR1L while the timer is running from an external asynchronous clock, will guarantee a valid read (taken care of in hardware). However, the user should keep in mind that reading the 16-bit timer in two 8-bit values itself, poses certain problems, since the timer may overflow between the reads. For writes, it is recommended that the user simply stop the timer and write the desired values. A write contention may occur by writing to the timer registers, while the register is incrementing. This may produce an unpredictable value in the timer register. Reading the 16-bit value requires some care. Examples 12-2 and 12-3 in the PICmicroTM Mid-Range MCU Family Reference Manual (DS33023) show how to read and write Timer1 when it is running in Asynchronous mode.
6.6
Resetting Timer1 using a CCP Trigger Output
If the CCP1 or CCP2 module is configured in Compare mode to generate a "special event trigger" (CCP1M3:CCP1M0 = 1011), this signal will reset Timer1. Note: The special event triggers from the CCP1 and CCP2 modules will not set interrupt flag bit TMR1IF (PIR1<0>).
6.5
Timer1 Oscillator
Timer1 must be configured for either Timer or Synchronized Counter mode to take advantage of this feature. If Timer1 is running in Asynchronous Counter mode, this RESET operation may not work. In the event that a write to Timer1 coincides with a special event trigger from CCP1 or CCP2, the write will take precedence. In this mode of operation, the CCPRxH:CCPRxL register pair effectively becomes the period register for Timer1.
A crystal oscillator circuit is built-in between pins T1OSI (input) and T1OSO (amplifier output). It is enabled by setting control bit, T1OSCEN (T1CON<3>). The oscillator is a low power oscillator, rated up to 200 kHz. It will continue to run during SLEEP. It is primarily intended for use with a 32 kHz crystal. Table 6-1 shows the capacitor selection for the Timer1 oscillator. The Timer1 oscillator is identical to the LP oscillator. The user must provide a software time delay to ensure proper oscillator start-up.
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6.7 Resetting of Timer1 Register Pair (TMR1H, TMR1L) 6.8 Timer1 Prescaler
The prescaler counter is cleared on writes to the TMR1H or TMR1L registers.
TMR1H and TMR1L registers are not reset to 00h on a POR, or any other RESET, except by the CCP1 and CCP2 special event triggers. T1CON register is reset to 00h on a Power-on Reset, or a Brown-out Reset, which shuts off the timer and leaves a 1:1 prescale. In all other RESETS, the register is unaffected.
TABLE 6-2:
Address
REGISTERS ASSOCIATED WITH TIMER1 AS A TIMER/COUNTER
Name Bit 7 GIE PSPIF(1) Bit 6 PEIE ADIF Bit 5 TMR0IE RCIF RCIE Bit 4 INTE TXIF TXIE Bit 3 RBIE SSPIF SSPIE Bit 2 TMR0IF CCP1IF CCP1IE Bit 1 INTF TMR2IF TMR2IE Bit 0 RBIF Value on: POR, BOR Value on all other RESETS
0Bh,8Bh, INTCON 10Bh, 18Bh 0Ch 8Ch 0Eh 0Fh 10h Legend: PIR1 PIE1 TMR1L
0000 000x 0000 000u
TMR1IF 0000 0000 0000 0000 TMR1IE 0000 0000 0000 0000
xxxx xxxx uuuu uuuu xxxx xxxx uuuu uuuu
PSPIE(1) ADIE
Holding Register for the Least Significant Byte of the 16-bit TMR1 Register
TMR1H Holding Register for the Most Significant Byte of the 16-bit TMR1 Register T1CON -- --
T1CKPS1 T1CKPS0 T1OSCEN T1SYNC TMR1CS TMR1ON --00 0000 --uu uuuu
x = unknown, u = unchanged, - = unimplemented, read as '0'. Shaded cells are not used by the Timer1 module.
Note 1: Bits PSPIE and PSPIF are reserved on the 28-pin devices; always maintain these bits clear.
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7.0 TIMER2 MODULE
Register 7-1 shows the Timer2 control register. Additional information on timer modules is available in the PICmicroTM Mid-Range MCU Family Reference Manual (DS33023). Timer2 is an 8-bit timer with a prescaler and a postscaler. It can be used as the PWM time-base for the PWM mode of the CCP module(s). The TMR2 register is readable and writable, and is cleared on any device RESET. The input clock (FOSC/4) has a prescale option of 1:1, 1:4, or 1:16, selected by control bits T2CKPS1:T2CKPS0 (T2CON<1:0>). The Timer2 module has an 8-bit period register, PR2. Timer2 increments from 00h until it matches PR2 and then resets to 00h on the next increment cycle. PR2 is a readable and writable register. The PR2 register is initialized to FFh upon RESET. The match output of TMR2 goes through a 4-bit postscaler (which gives a 1:1 to 1:16 scaling inclusive) to generate a TMR2 interrupt (latched in flag bit TMR2IF, (PIR1<1>)). Timer2 can be shut-off by clearing control bit, TMR2ON (T2CON<2>), to minimize power consumption.
FIGURE 7-1:
Sets Flag bit TMR2IF TMR2 Output(1) RESET Postscaler 1:1 to 1:16 4 T2OUTPS3: T2OUTPS0
TIMER2 BLOCK DIAGRAM
TMR2 Reg Comparator
Prescaler 1:1, 1:4, 1:16 2 T2CKPS1: T2CKPS0
FOSC/4
EQ
PR2 Reg
Note 1: TMR2 register output can be software selected by the SSP module as a baud clock.
REGISTER 7-1:
T2CON: TIMER2 CONTROL REGISTER (ADDRESS 12h)
U-0 -- bit 7 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 bit 0 TOUTPS3 TOUTPS2 TOUTPS1 TOUTPS0 TMR2ON T2CKPS1 T2CKPS0
bit 7 bit 6-3
Unimplemented: Read as '0' TOUTPS3:TOUTPS0: Timer2 Output Postscale Select bits 0000 = 1:1 Postscale 0001 = 1:2 Postscale 0010 = 1:3 Postscale * * * 1111 = 1:16 Postscale TMR2ON: Timer2 On bit 1 = Timer2 is on 0 = Timer2 is off T2CKPS1:T2CKPS0: Timer2 Clock Prescale Select bits 00 = Prescaler is 1 01 = Prescaler is 4 1x = Prescaler is 16 Legend: R = Readable bit - n = Value at POR W = Writable bit '1' = Bit is set U = Unimplemented bit, read as `0' '0' = Bit is cleared x = Bit is unknown
bit 2
bit 1-0
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7.1 Timer2 Prescaler and Postscaler 7.2 Output of TMR2
The prescaler and postscaler counters are cleared when any of the following occurs: * a write to the TMR2 register * a write to the T2CON register * any device RESET (POR, MCLR Reset, WDT Reset, or BOR) TMR2 is not cleared when T2CON is written. The output of TMR2 (before the postscaler) is fed to the SSP module, which optionally uses it to generate shift clock.
TABLE 7-1:
Address
REGISTERS ASSOCIATED WITH TIMER2 AS A TIMER/COUNTER
Bit 7 GIE PSPIF(1) PSPIE(1) -- Bit 6 PEIE ADIF ADIE Bit 5 TMR0IE RCIF RCIE Bit 4 INTE TXIF TXIE Bit 3 RBIE SSPIF SSPIE Bit 2 TMR0IF CCP1IF CCP1IE Bit 1 INTF TMR2IF TMR2IE Bit 0 RBIF Value on: POR, BOR Value on all other RESETS
Name
0Bh, 8Bh, INTCON 10Bh, 18Bh 0Ch 8Ch 11h 12h 92h Legend: PIR1 PIE1 TMR2 T2CON PR2
0000 000x 0000 000u
TMR1IF 0000 0000 0000 0000 TMR1IE 0000 0000 0000 0000
0000 0000 0000 0000 1111 1111 1111 1111
Timer2 Module's Register Timer2 Period Register
TOUTPS3 TOUTPS2 TOUTPS1 TOUTPS0 TMR2ON T2CKPS1 T2CKPS0 -000 0000 -000 0000
x = unknown, u = unchanged, - = unimplemented, read as '0'. Shaded cells are not used by the Timer2 module.
Note 1: Bits PSPIE and PSPIF are reserved on 28-pin devices; always maintain these bits clear.
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8.0 CAPTURE/COMPARE/PWM MODULES
CCP2 Module: Capture/Compare/PWM Register2 (CCPR2) is comprised of two 8-bit registers: CCPR2L (low byte) and CCPR2H (high byte). The CCP2CON register controls the operation of CCP2. The special event trigger is generated by a compare match and will reset Timer1 and start an A/D conversion (if the A/D module is enabled). Additional information on CCP modules is available in the PICmicroTM Mid-Range MCU Family Reference Manual (DS33023) and in application note AN594, "Using the CCP Modules" (DS00594).
Each Capture/Compare/PWM (CCP) module contains a 16-bit register which can operate as a: * 16-bit Capture register * 16-bit Compare register * PWM Master/Slave Duty Cycle register Both the CCP1 and CCP2 modules are identical in operation, with the exception being the operation of the special event trigger. Table 8-1 and Table 8-2 show the resources and interactions of the CCP module(s). In the following sections, the operation of a CCP module is described with respect to CCP1. CCP2 operates the same as CCP1, except where noted. CCP1 Module: Capture/Compare/PWM Register1 (CCPR1) is comprised of two 8-bit registers: CCPR1L (low byte) and CCPR1H (high byte). The CCP1CON register controls the operation of CCP1. The special event trigger is generated by a compare match and will reset Timer1.
TABLE 8-1:
CCP MODE - TIMER RESOURCES REQUIRED
Timer Resource Timer1 Timer1 Timer2
CCP Mode Capture Compare PWM
TABLE 8-2:
INTERACTION OF TWO CCP MODULES
Interaction Same TMR1 time-base The compare should be configured for the special event trigger, which clears TMR1 The compare(s) should be configured for the special event trigger, which clears TMR1 The PWMs will have the same frequency and update rate (TMR2 interrupt) None None
CCPx Mode CCPy Mode Capture Capture Compare PWM PWM PWM Capture Compare Compare PWM Capture Compare
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REGISTER 8-1: CCP1CON REGISTER/CCP2CON REGISTER (ADDRESS: 17h/1Dh)
U-0 -- bit 7 bit 7-6 bit 5-4 Unimplemented: Read as '0' CCPxX:CCPxY: PWM Least Significant bits Capture mode: Unused Compare mode: Unused PWM mode: These bits are the two LSbs of the PWM duty cycle. The eight MSbs are found in CCPRxL. CCPxM3:CCPxM0: CCPx Mode Select bits 0000 = Capture/Compare/PWM disabled (resets CCPx module) 0100 = Capture mode, every falling edge 0101 = Capture mode, every rising edge 0110 = Capture mode, every 4th rising edge 0111 = Capture mode, every 16th rising edge 1000 = Compare mode, set output on match (CCPxIF bit is set) 1001 = Compare mode, clear output on match (CCPxIF bit is set) 1010 = Compare mode, generate software interrupt on match (CCPxIF bit is set, CCPx pin is unaffected) 1011 = Compare mode, trigger special event (CCPxIF bit is set, CCPx pin is unaffected); CCP1 resets TMR1; CCP2 resets TMR1 and starts an A/D conversion (if A/D module is enabled) 11xx = PWM mode Legend: R = Readable bit - n = Value at POR W = Writable bit '1' = Bit is set U = Unimplemented bit, read as `0' '0' = Bit is cleared x = Bit is unknown U-0 -- R/W-0 CCPxX R/W-0 CCPxY R/W-0 CCPxM3 R/W-0 CCPxM2 R/W-0 CCPxM1 R/W-0 CCPxM0 bit 0
bit 3-0
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8.1 Capture Mode
8.1.2 TIMER1 MODE SELECTION
In Capture mode, CCPR1H:CCPR1L captures the 16-bit value of the TMR1 register when an event occurs on pin RC2/CCP1. An event is defined as one of the following: * * * * Every falling edge Every rising edge Every 4th rising edge Every 16th rising edge Timer1 must be running in Timer mode, or Synchronized Counter mode, for the CCP module to use the capture feature. In Asynchronous Counter mode, the capture operation may not work.
8.1.3
SOFTWARE INTERRUPT
The type of event is configured by control bits CCP1M3:CCP1M0 (CCPxCON<3:0>). When a capture is made, the interrupt request flag bit, CCP1IF (PIR1<2>) is set. The interrupt flag must be cleared in software. If another capture occurs before the value in register CCPR1 is read, the old captured value is overwritten by the new value.
When the Capture mode is changed, a false capture interrupt may be generated. The user should keep bit CCP1IE (PIE1<2>) clear to avoid false interrupts and should clear the flag bit, CCP1IF, following any such change in operating mode.
8.1.4
CCP PRESCALER
8.1.1
CCP PIN CONFIGURATION
There are four prescaler settings, specified by bits CCP1M3:CCP1M0. Whenever the CCP module is turned off, or the CCP module is not in Capture mode, the prescaler counter is cleared. Any RESET will clear the prescaler counter. Switching from one capture prescaler to another may generate an interrupt. Also, the prescaler counter will not be cleared, therefore, the first capture may be from a non-zero prescaler. Example 8-1 shows the recommended method for switching between capture prescalers. This example also clears the prescaler counter and will not generate the "false" interrupt.
In Capture mode, the RC2/CCP1 pin should be configured as an input by setting the TRISC<2> bit. Note: If the RC2/CCP1 pin is configured as an output, a write to the port can cause a capture condition.
FIGURE 8-1:
CAPTURE MODE OPERATION BLOCK DIAGRAM
Set Flag bit CCP1IF (PIR1<2>)
EXAMPLE 8-1:
CLRF MOVLW
RC2/CCP1 pin
CHANGING BETWEEN CAPTURE PRESCALERS
Prescaler / 1, 4, 16
CCPR1H and edge detect Capture Enable TMR1H CCP1CON<3:0> Qs
CCPR1L
MOVWF
CCP1CON ; Turn CCP module off NEW_CAPT_PS ; Load the W reg with ; the new prescaler ; move value and CCP ON CCP1CON ; Load CCP1CON with this ; value
TMR1L
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8.2 Compare Mode
8.2.2 TIMER1 MODE SELECTION
In Compare mode, the 16-bit CCPR1 register value is constantly compared against the TMR1 register pair value. When a match occurs, the RC2/CCP1 pin is: * Driven high * Driven low * Remains unchanged The action on the pin is based on the value of control bits, CCP1M3:CCP1M0 (CCP1CON<3:0>). At the same time, interrupt flag bit, CCP1IF is set. Timer1 must be running in Timer mode, or Synchronized Counter mode, if the CCP module is using the compare feature. In Asynchronous Counter mode, the compare operation may not work.
8.2.3
SOFTWARE INTERRUPT MODE
When Generate Software Interrupt mode is chosen, the CCP1 pin is not affected. The CCPIF bit is set, causing a CCP interrupt (if enabled).
8.2.4 FIGURE 8-2: COMPARE MODE OPERATION BLOCK DIAGRAM
SPECIAL EVENT TRIGGER
In this mode, an internal hardware trigger is generated, which may be used to initiate an action. The special event trigger output of CCP1 resets the TMR1 register pair. This allows the CCPR1 register to effectively be a 16-bit programmable period register for Timer1. The special event trigger output of CCP2 resets the TMR1 register pair and starts an A/D conversion (if the A/D module is enabled). Note: The special event trigger from the CCP1and CCP2 modules will not set interrupt flag bit TMR1IF (PIR1<0>).
Special event trigger will: reset Timer1, but not set interrupt flag bit TMR1IF (PIR1<0>), and set bit GO/DONE (ADCON0<2>). Special Event Trigger Set Flag bit CCP1IF (PIR1<2>) RC2/CCP1 pin Q S R TRISC<2> Output Enable Output Logic Match CCPR1H CCPR1L Comparator TMR1H TMR1L
CCP1CON<3:0> Mode Select
8.2.1
CCP PIN CONFIGURATION
The user must configure the RC2/CCP1 pin as an output by clearing the TRISC<2> bit. Note: Clearing the CCP1CON register will force the RC2/CCP1 compare output latch to the default low level. This is not the PORTC I/O data latch.
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8.3 PWM Mode (PWM)
8.3.1 PWM PERIOD
In Pulse Width Modulation mode, the CCPx pin produces up to a 10-bit resolution PWM output. Since the CCP1 pin is multiplexed with the PORTC data latch, the TRISC<2> bit must be cleared to make the CCP1 pin an output. Note: Clearing the CCP1CON register will force the CCP1 PWM output latch to the default low level. This is not the PORTC I/O data latch. The PWM period is specified by writing to the PR2 register. The PWM period can be calculated using the following formula: PWM period = [(PR2) + 1] * 4 * TOSC * (TMR2 prescale value) PWM frequency is defined as 1 / [PWM period]. When TMR2 is equal to PR2, the following three events occur on the next increment cycle: * TMR2 is cleared * The CCP1 pin is set (exception: if PWM duty cycle = 0%, the CCP1 pin will not be set) * The PWM duty cycle is latched from CCPR1L into CCPR1H Note: The Timer2 postscaler (see Section 7.1) is not used in the determination of the PWM frequency. The postscaler could be used to have a servo update rate at a different frequency than the PWM output.
Figure 8-3 shows a simplified block diagram of the CCP module in PWM mode. For a step-by-step procedure on how to set up the CCP module for PWM operation, see Section 8.3.3.
FIGURE 8-3:
SIMPLIFIED PWM BLOCK DIAGRAM
CCP1CON<5:4>
Duty Cycle Registers CCPR1L
8.3.2
CCPR1H (Slave) RC2/CCP1 Comparator R Q
PWM DUTY CYCLE
TMR2
(Note 1) S
The PWM duty cycle is specified by writing to the CCPR1L register and to the CCP1CON<5:4> bits. Up to 10-bit resolution is available. The CCPR1L contains the eight MSbs and the CCP1CON<5:4> contains the two LSbs. This 10-bit value is represented by CCPR1L:CCP1CON<5:4>. The following equation is used to calculate the PWM duty cycle in time: PWM duty cycle =(CCPR1L:CCP1CON<5:4>) * TOSC * (TMR2 prescale value) CCPR1L and CCP1CON<5:4> can be written to at any time, but the duty cycle value is not latched into CCPR1H until after a match between PR2 and TMR2 occurs (i.e., the period is complete). In PWM mode, CCPR1H is a read-only register. The CCPR1H register and a 2-bit internal latch are used to double buffer the PWM duty cycle. This double buffering is essential for glitch-free PWM operation. When the CCPR1H and 2-bit latch match TMR2, concatenated with an internal 2-bit Q clock, or 2 bits of the TMR2 prescaler, the CCP1 pin is cleared. The maximum PWM resolution (bits) for a given PWM frequency is given by the formula: FOSC log( FPWM log(2)
Comparator Clear Timer, CCP1 pin and latch D.C.
TRISC<2>
PR2
Note 1: The 8-bit timer is concatenated with 2-bit internal Q clock, or 2 bits of the prescaler, to create 10-bit timebase.
A PWM output (Figure 8-4) has a time-base (period) and a time that the output stays high (duty cycle). The frequency of the PWM is the inverse of the period (1/period).
FIGURE 8-4:
Period
PWM OUTPUT
Duty Cycle TMR2 = PR2 TMR2 = Duty Cycle TMR2 = PR2
Resolution
=
)
bits
Note:
If the PWM duty cycle value is longer than the PWM period, the CCP1 pin will not be cleared.
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8.3.3 SETUP FOR PWM OPERATION
The following steps should be taken when configuring the CCP module for PWM operation: 1. 2. 3. 4. 5. Set the PWM period by writing to the PR2 register. Set the PWM duty cycle by writing to the CCPR1L register and CCP1CON<5:4> bits. Make the CCP1 pin an output by clearing the TRISC<2> bit. Set the TMR2 prescale value and enable Timer2 by writing to T2CON. Configure the CCP1 module for PWM operation.
TABLE 8-3:
EXAMPLE PWM FREQUENCIES AND RESOLUTIONS AT 20 MHz
1.22 kHz 16 0xFFh 10 4.88 kHz 4 0xFFh 10 19.53 kHz 1 0xFFh 10 78.12kHz 1 0x3Fh 8 156.3 kHz 1 0x1Fh 7 208.3 kHz 1 0x17h 5.5
PWM Frequency Timer Prescaler (1, 4, 16) PR2 Value Maximum Resolution (bits)
TABLE 8-4:
Address
REGISTERS ASSOCIATED WITH CAPTURE, COMPARE, AND TIMER1
Name Bit 7 GIE PSPIF(1) -- PSPIE --
(1)
Bit 6 PEIE ADIF -- ADIE --
Bit 5 TMR0IE RCIF -- RCIE --
Bit 4 INTE TXIF -- TXIE --
Bit 3 RBIE SSPIF -- SSPIE --
Bit 2 TMR0IF CCP1IF -- CCP1IE --
Bit 1 INTF TMR2IF -- TMR2IE --
Bit 0 RBIF
Value on: POR, BOR
Value on all other RESETS
0Bh,8Bh, INTCON 10Bh, 18Bh 0Ch 0Dh 8Ch 8Dh 87h 0Eh 0Fh 10h 15h 16h 17h 1Bh 1Ch 1Dh Legend: PIR1 PIR2 PIE1 PIE2 TRISC TMR1L TMR1H T1CON CCPR1L CCPR1H CCP1CON CCPR2L CCPR2H CCP2CON
0000 000x 0000 000u
TMR1IF 0000 0000 0000 0000 CCP2IF ---- ---0 ---- ---0 TMR1IE 0000 0000 0000 0000 CCP2IE ---- ---0 ---- ---0
1111 1111 1111 1111 xxxx xxxx uuuu uuuu xxxx xxxx uuuu uuuu
PORTC Data Direction Register Holding Register for the Least Significant Byte of the 16-bit TMR1 Register Holding Register for the Most Significant Byte of the 16-bit TMR1 Register -- --
T1CKPS1 T1CKPS0 T1OSCEN T1SYNC TMR1CS TMR1ON --00 0000 --uu uuuu
xxxx xxxx uuuu uuuu xxxx xxxx uuuu uuuu
Capture/Compare/PWM Register1 (LSB) Capture/Compare/PWM Register1 (MSB) -- -- CCP1X CCP1Y
CCP1M3 CCP1M2 CCP1M1 CCP1M0 --00 0000 --00 0000
xxxx xxxx uuuu uuuu xxxx xxxx uuuu uuuu
Capture/Compare/PWM Register2 (LSB) Capture/Compare/PWM Register2 (MSB) -- -- CCP2X CCP2Y
CCP2M3 CCP2M2 CCP2M1 CCP2M0 --00 0000 --00 0000
x = unknown, u = unchanged, - = unimplemented, read as '0'. Shaded cells are not used by Capture and Timer1.
Note 1: The PSP is not implemented on 28-pin devices; always maintain these bits clear.
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TABLE 8-5:
Address
REGISTERS ASSOCIATED WITH PWM AND TIMER2
Name Bit 7 GIE PSPIF(1) -- PSPIE(1) -- Bit 6 PEIE ADIF -- ADIE -- Bit 5 TMR0IE RCIF -- RCIE -- Bit 4 INTE TXIF -- TXIE -- Bit 3 RBIE SSPIF -- SSPIE -- Bit 2 TMR0IF CCP1IF -- CCP1IE -- Bit 1 INTF TMR2IF -- TMR2IE -- Bit 0 RBIF Value on: POR, BOR Value on all other RESETS
0Bh,8Bh, INTCON 10Bh, 18Bh 0Ch 0Dh 8Ch 8Dh 87h 11h 92h 12h 15h 16h 17h 1Bh 1Ch 1Dh PIR1 PIR2 PIE1 PIE2 TRISC TMR2 PR2 T2CON CCPR1L CCPR1H CCP1CON CCPR2L CCPR2H CCP2CON
0000 000x 0000 000u
TMR1IF 0000 0000 0000 0000 CCP2IF ---- ---0 ---- ---0 TMR1IE 0000 0000 0000 0000 CCP2IE ---- ---0 ---- ---0
1111 1111 1111 1111 0000 0000 0000 0000 1111 1111 1111 1111
PORTC Data Direction Register Timer2 Module's Register Timer2 Module's Period Register --
TOUTPS3 TOUTPS2 TOUTPS1 TOUTPS0 TMR2ON T2CKPS1 T2CKPS0 -000 0000 -000 0000
xxxx xxxx uuuu uuuu xxxx xxxx uuuu uuuu
Capture/Compare/PWM Register1 (LSB) Capture/Compare/PWM Register1 (MSB) -- -- CCP1X CCP1Y
CCP1M3 CCP1M2 CCP1M1 CCP1M0 --00 0000 --00 0000
xxxx xxxx uuuu uuuu xxxx xxxx uuuu uuuu
Capture/Compare/PWM Register2 (LSB) Capture/Compare/PWM Register2 (MSB) -- -- CCP2X CCP2Y
CCP2M3 CCP2M2 CCP2M1 CCP2M0 --00 0000 --00 0000
Legend: x = unknown, u = unchanged, - = unimplemented, read as '0'. Shaded cells are not used by PWM and Timer2. Note 1: Bits PSPIE and PSPIF are reserved on 28-pin devices; always maintain these bits clear.
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NOTES:
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9.0 MASTER SYNCHRONOUS SERIAL PORT (MSSP) MODULE
Master SSP (MSSP) Module Overview
RC4/ SDI/ SDA SSPSR reg RC5/SDO bit0 Shift Clock
FIGURE 9-1:
MSSP BLOCK DIAGRAM (SPI MODE)
Internal Data Bus Read SSPBUF reg Write
9.1
The Master Synchronous Serial Port (MSSP) module is a serial interface, useful for communicating with other peripheral or microcontroller devices. These peripheral devices may be serial EEPROMs, shift registers, display drivers, A/D converters, etc. The MSSP module can operate in one of two modes: * Serial Peripheral Interface (SPI) * Inter-Integrated Circuit (I2C) - Full Master Mode - Slave mode (with general address call) The I2C interface supports the following modes in hardware: * Master mode * Multi-Master mode * Slave mode
Peripheral OE RA5/ SS/ AN4
SS Control Enable Edge Select 2 Clock Select
9.2
Control Registers
The MSSP module has three associated registers. These include a status register (SSPSTAT) and two control registers (SSPCON and SSPCON2). The uses of these registers and their individual configuration bits differ significantly, depending on whether the MSSP module is operated in SPI or I2C mode. Additional details are provided under the individual sections.
RC3/ SCK/ SCL/ LVDIN
SSPM3:SSPM0 SMP:CKE 4 TMR2 output 2 2 Edge Select Prescaler TOSC 4, 16, 64
(
)
Data to TX/RX in SSPSR TRIS bit
9.3
SPI Mode
Note:
The SPI mode allows 8 bits of data to be synchronously transmitted and received simultaneously. All four modes of SPI are supported. To accomplish communication, typically three pins are used: * Serial Data Out (SDO) - RC5/SDO * Serial Data In (SDI) - RC4/SDI/SDA * Serial Clock (SCK) - RC3/SCK/SCL/LVDIN Additionally a fourth pin may be used when in a Slave mode of operation: * Slave Select (SS) - RA5/SS/AN4 Figure 9-1 shows the block diagram of the MSSP module when operating in SPI mode.
When the SPI is in Slave mode with SS pin control enabled (SSPCON<3:0> = 0100), the state of the SS pin can affect the state read back from the TRISC<5> bit. The Peripheral OE signal from the SSP module into PORTC, controls the state that is read back from the TRISC<5> bit (see Section 4.3 for information on PORTC). If Read-Modify-Write instructions, such as BSF, are performed on the TRISC register while the SS pin is high, this will cause the TRISC<5> bit to be set, thus disabling the SDO output.
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9.3.1 REGISTERS
The MSSP module has four registers for SPI mode operation. These are: * * * * MSSP Control Register (SSPCON) MSSP Status Register (SSPSTAT) Serial Receive/Transmit Buffer (SSPBUF) MSSP Shift Register (SSPSR) - Not directly accessible SSPSR is the shift register used for shifting data in or out. SSPBUF is the buffer register to which data bytes are written to or read from. In receive operations, SSPSR and SSPBUF together create a double-buffered receiver. When SSPSR receives a complete byte, it is transferred to SSPBUF and the SSPIF interrupt is set. During transmission, the SSPBUF is not double buffered. A write to SSPBUF will write to both SSPBUF and SSPSR.
SSPCON and SSPSTAT are the control and status registers in SPI mode operation. The SSPCON register is readable and writable. The lower 6 bits of the SSPSTAT are read only. The upper two bits of the SSPSTAT are read/write.
REGISTER 9-1:
SSPSTAT: MSSP STATUS REGISTER (SPI MODE) (ADDRESS 94h)
R/W-0 SMP bit 7 R/W-0 CKE R-0 D/A R-0 P R-0 S R-0 R/W R-0 UA R-0 BF bit 0
bit 7
SMP: Sample bit SPI Master mode: 1 = Input data sampled at end of data output time 0 = Input data sampled at middle of data output time SPI Slave mode: SMP must be cleared when SPI is used in Slave mode CKE: SPI Clock Edge Select bit When CKP = 0: 1 = Data transmitted on rising edge of SCK 0 = Data transmitted on falling edge of SCK When CKP = 1: 1 = Data transmitted on falling edge of SCK 0 = Data transmitted on rising edge of SCK D/A: Data/Address bit Used in I2C mode only P: STOP bit Used in I2C mode only. This bit is cleared when the MSSP module is disabled, SSPEN is cleared. S: START bit Used in I2C mode only R/W: Read/Write bit information Used in I2C mode only UA: Update Address bit Used in I2C mode only BF: Buffer Full Status bit (Receive mode only) 1 = Receive complete, SSPBUF is full 0 = Receive not complete, SSPBUF is empty Legend: R = Readable bit - n = Value at POR W = Writable bit '1' = Bit is set U = Unimplemented bit, read as `0' '0' = Bit is cleared x = Bit is unknown
bit 6
bit 5 bit 4 bit 3 bit 2 bit 1 bit 0
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REGISTER 9-2: SSPCON: MSSP CONTROL REGISTER1 (SPI MODE) (ADDRESS 14h)
R/W-0 WCOL bit 7 bit 7 WCOL: Write Collision Detect bit (Transmit mode only) 1 = The SSPBUF register is written while it is still transmitting the previous word. (Must be cleared in software.) 0 = No collision SSPOV: Receive Overflow Indicator bit SPI Slave mode: 1 = A new byte is received while the SSPBUF register is still holding the previous data. In case of overflow, the data in SSPSR is lost. Overflow can only occur in Slave mode.The user must read the SSPBUF, even if only transmitting data, to avoid setting overflow. (Must be cleared in software.) 0 = No overflow Note: bit 5 In Master mode, the overflow bit is not set, since each new reception (and transmission) is initiated by writing to the SSPBUF register. R/W-0 SSPOV R/W-0 SSPEN R/W-0 CKP R/W-0 SSPM3 R/W-0 SSPM2 R/W-0 SSPM1 R/W-0 SSPM0 bit 0
bit 6
SSPEN: Synchronous Serial Port Enable bit 1 = Enables serial port and configures SCK, SDO, SDI, and SS as serial port pins 0 = Disables serial port and configures these pins as I/O port pins Note: When enabled, these pins must be properly configured as input or output. CKP: Clock Polarity Select bit 1 = IDLE state for clock is a high level 0 = IDLE state for clock is a low level SSPM3:SSPM0: Synchronous Serial Port Mode Select bits 0101 = SPI Slave mode, clock = SCK pin. SS pin control disabled. SS can be used as I/O pin 0100 = SPI Slave mode, clock = SCK pin. SS pin control enabled. 0011 = SPI Master mode, clock = TMR2 output/2 0010 = SPI Master mode, clock = FOSC/64 0001 = SPI Master mode, clock = FOSC/16 0000 = SPI Master mode, clock = FOSC/4 Note: Bit combinations not specifically listed here are either reserved, or implemented in I2C mode only.
bit 4
bit 3-0
Legend: R = Readable bit - n = Value at POR W = Writable bit '1' = Bit is set U = Unimplemented bit, read as `0' '0' = Bit is cleared x = Bit is unknown
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9.3.2 OPERATION
When initializing the SPI, several options need to be specified. This is done by programming the appropriate control bits (SSPCON<5:0>) and SSPSTAT<7:6>. These control bits allow the following to be specified: Master mode (SCK is the clock output) Slave mode (SCK is the clock input) Clock Polarity (IDLE state of SCK) Data input sample phase (middle or end of data output time) * Clock edge (output data on rising/falling edge of SCK) * Clock Rate (Master mode only) * Slave Select mode (Slave mode only) The MSSP consists of a transmit/receive Shift Register (SSPSR) and a buffer register (SSPBUF). The SSPSR shifts the data in and out of the device, MSb first. The SSPBUF holds the data that was written to the SSPSR, until the received data is ready. Once the 8 bits of data have been received, that byte is moved to the SSPBUF register. Then, the buffer full detect bit, BF (SSPSTAT<0>), and the interrupt flag bit, SSPIF, are set. This double buffering of the received data (SSPBUF) allows the next byte to start reception before reading the data that was just received. Any write to the * * * * SSPBUF register during transmission/reception of data will be ignored, and the write collision detect bit, WCOL (SSPCON<7>), will be set. User software must clear the WCOL bit so that it can be determined if the following write(s) to the SSPBUF register completed successfully. When the application software is expecting to receive valid data, the SSPBUF should be read before the next byte of data to transfer is written to the SSPBUF. Buffer full bit, BF (SSPSTAT<0>), indicates when SSPBUF has been loaded with the received data (transmission is complete). When the SSPBUF is read, the BF bit is cleared. This data may be irrelevant if the SPI is only a transmitter. Generally, the MSSP Interrupt is used to determine when the transmission/reception has completed. The SSPBUF must be read and/or written. If the interrupt method is not going to be used, then software polling can be done to ensure that a write collision does not occur. Example 9-1 shows the loading of the SSPBUF (SSPSR) for data transmission. The SSPSR is not directly readable or writable, and can only be accessed by addressing the SSPBUF register. Additionally, the MSSP status register (SSPSTAT) indicates the various status conditions.
EXAMPLE 9-1:
LOADING THE SSPBUF (SSPSR) REGISTER
;Has data been received(transmit complete)? ;No ;WREG reg = contents of SSPBUF ;Save in user RAM, if data is meaningful ;W reg = contents of TXDATA ;New data to xmit
LOOP BTFSS SSPSTAT, BF BRA LOOP MOVF SSPBUF, W MOVWF RXDATA MOVF TXDATA, W MOVWF SSPBUF
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9.3.3 ENABLING SPI I/O 9.3.4 TYPICAL CONNECTION
To enable the serial port, SSP Enable bit, SSPEN (SSPCON<5>), must be set. To reset or reconfigure SPI mode, clear the SSPEN bit, re-initialize the SSPCON registers, and then set the SSPEN bit. This configures the SDI, SDO, SCK, and SS pins as serial port pins. For the pins to behave as the serial port function, some must have their data direction bits (in the TRIS register) appropriately programmed. That is: * SDI is automatically controlled by the SPI module * SDO must have TRISC<5> bit cleared * SCK (Master mode) must have TRISC<3> bit cleared * SCK (Slave mode) must have TRISC<3> bit set * SS must have TRISC<4> bit set Any serial port function that is not desired may be overridden by programming the corresponding data direction (TRIS) register to the opposite value. Figure 9-2 shows a typical connection between two microcontrollers. The master controller (Processor 1) initiates the data transfer by sending the SCK signal. Data is shifted out of both shift registers on their programmed clock edge, and latched on the opposite edge of the clock. Both processors should be programmed to same Clock Polarity (CKP), then both controllers would send and receive data at the same time. Whether the data is meaningful (or dummy data) depends on the application software. This leads to three scenarios for data transmission: * Master sends data -- Slave sends dummy data * Master sends data -- Slave sends data * Master sends dummy data -- Slave sends data
FIGURE 9-2:
SPI MASTER/SLAVE CONNECTION
SPI Master SSPM3:SSPM0 = 00xxb SDO SDI
SPI Slave SSPM3:SSPM0 = 010xb
Serial Input Buffer (SSPBUF)
Serial Input Buffer (SSPBUF)
Shift Register (SSPSR) MSb LSb
SDI
SDO
Shift Register (SSPSR) MSb LSb
SCK PROCESSOR 1
Serial Clock
SCK PROCESSOR 2
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9.3.5 MASTER MODE
The master can initiate the data transfer at any time because it controls the SCK. The master determines when the slave (Processor 2, Figure 9-2) is to broadcast data by the software protocol. In Master mode, the data is transmitted/received as soon as the SSPBUF register is written to. If the SPI is only going to receive, the SDO output could be disabled (programmed as an input). The SSPSR register will continue to shift in the signal present on the SDI pin at the programmed clock rate. As each byte is received, it will be loaded into the SSPBUF register as if a normal received byte (interrupts and status bits appropriately set). This could be useful in receiver applications as a "Line Activity Monitor" mode. The clock polarity is selected by appropriately programming the CKP bit (SSPCON<4>). This then, would give waveforms for SPI communication as shown in Figure 9-3, Figure 9-5, and Figure 9-6, where the MSB is transmitted first. In Master mode, the SPI clock rate (bit rate) is user programmable to be one of the following: * * * * FOSC/4 (or TCY) FOSC/16 (or 4 * TCY) FOSC/64 (or 16 * TCY) Timer2 output/2
This allows a maximum data rate (at 40 MHz) of 10.00 Mbps. Figure 9-3 shows the waveforms for Master mode. When the CKE bit is set, the SDO data is valid before there is a clock edge on SCK. The change of the input sample is shown based on the state of the SMP bit. The time when the SSPBUF is loaded with the received data is shown.
FIGURE 9-3:
Write to SSPBUF SCK (CKP = 0 CKE = 0) SCK (CKP = 1 CKE = 0) SCK (CKP = 0 CKE = 1) SCK (CKP = 1 CKE = 1) SDO (CKE = 0) SDO (CKE = 1) SDI (SMP = 0) Input Sample (SMP = 0) SDI (SMP = 1) Input Sample (SMP = 1) SSPIF SSPSR to SSPBUF
SPI MODE WAVEFORM (MASTER MODE)
4 clock modes
bit7 bit7
bit6 bit6
bit5 bit5
bit4 bit4
bit3 bit3
bit2 bit2
bit1 bit1
bit0 bit0
bit7
bit0
bit7
bit0
Next Q4 cycle after Q2
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PIC16F87XA
9.3.6 SLAVE MODE
In Slave mode, the data is transmitted and received as the external clock pulses appear on SCK. When the last bit is latched, the SSPIF interrupt flag bit is set. While in Slave mode, the external clock is supplied by the external clock source on the SCK pin. This external clock must meet the minimum high and low times, as specified in the electrical specifications. While in SLEEP mode, the slave can transmit/receive data. When a byte is received, the device will wake-up from SLEEP. the SDO pin is no longer driven, even if in the middle of a transmitted byte, and becomes a floating output. External pull-up/pull-down resistors may be desirable, depending on the application. Note 1: When the SPI is in Slave Mode with SS pin control enabled (SSPCON<3:0> = 0100), the SPI module will reset if the SS pin is set to VDD. 2: If the SPI is used in Slave Mode with CKE set, then the SS pin control must be enabled. When the SPI module resets, the bit counter is forced to 0. This can be done by either forcing the SS pin to a high level or clearing the SSPEN bit. To emulate two-wire communication, the SDO pin can be connected to the SDI pin. When the SPI needs to operate as a receiver, the SDO pin can be configured as an input. This disables transmissions from the SDO. The SDI can always be left as an input (SDI function) since it cannot create a bus conflict.
9.3.7
SLAVE SELECT SYNCHRONIZATION
The SS pin allows a Synchronous Slave mode. The SPI must be in Slave mode with SS pin control enabled (SSPCON<3:0> = 04h). The pin must not be driven low for the SS pin to function as an input. The Data Latch must be high. When the SS pin is low, transmission and reception are enabled and the SDO pin is driven. When the SS pin goes high,
FIGURE 9-4:
SLAVE SYNCHRONIZATION WAVEFORM
SS
SCK (CKP = 0 CKE = 0) SCK (CKP = 1 CKE = 0)
Write to SSPBUF
SDO
bit7
bit6
bit7
bit0
SDI (SMP = 0) Input Sample (SMP = 0) SSPIF Interrupt Flag SSPSR to SSPBUF
bit0 bit7 bit7
Next Q4 cycle after Q2
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PIC16F87XA
FIGURE 9-5:
SS optional SCK (CKP = 0 CKE = 0) SCK (CKP = 1 CKE = 0) Write to SSPBUF SDO SDI (SMP = 0) Input Sample (SMP = 0) SSPIF Interrupt Flag SSPSR to SSPBUF bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0
SPI MODE WAVEFORM (SLAVE MODE WITH CKE = 0)
bit7
bit0
Next Q4 cycle after Q2
FIGURE 9-6:
SS not optional SCK (CKP = 0 CKE = 1) SCK (CKP = 1 CKE = 1) Write to SSPBUF SDO SDI (SMP = 0) Input Sample (SMP = 0) SSPIF Interrupt Flag SSPSR to SSPBUF
SPI MODE WAVEFORM (SLAVE MODE WITH CKE = 1)
bit7
bit6
bit5
bit4
bit3
bit2
bit1
bit0
bit7
bit0
Next Q4 cycle after Q2
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PIC16F87XA
9.3.8 SLEEP OPERATION 9.3.10 BUS MODE COMPATIBILITY
In Master mode, all module clocks are halted, and the transmission/reception will remain in that state until the device wakes from SLEEP. After the device returns to normal mode, the module will continue to transmit/ receive data. In Slave mode, the SPI transmit/receive shift register operates asynchronously to the device. This allows the device to be placed in SLEEP mode, and data to be shifted into the SPI transmit/receive shift register. When all 8-bits have been received, the MSSP interrupt flag bit will be set and if enabled, will wake the device from SLEEP. Table 9-1 shows the compatibility between the standard SPI modes and the states the CKP and CKE control bits.
TABLE 9-1:
SPI BUS MODES
Control Bits State CKP 0 0 1 1 CKE 1 0 1 0
Standard SPI Mode Terminology 0, 0, 1, 1, 0 1 0 1
9.3.9
EFFECTS OF A RESET
A reset disables the MSSP module and terminates the current transfer.
There is also a SMP bit which controls when the data is sampled.
TABLE 9-2:
Name INTCON PIR1 PIE1 IPR1 TRISC SSPBUF SSPCON TRISA SSPSTAT
REGISTERS ASSOCIATED WITH SPI OPERATION
Bit 7 Bit 6 PEIE/ GIEL ADIF ADIE ADIP Bit 5 TMR0IE RCIF RCIE RCIP Bit 4 INT0IE TXIF TXIE TXIP Bit 3 RBIE SSPIF SSPIE SSPIP Bit 2 TMR0IF CCP1IF CCP1IE CCP1IP Bit 1 INT0IF TMR2IF TMR2IE TMR2IP Bit 0 RBIF TMR1IF TMR1IE TMR1IP Value on POR, BOR Value on all other RESETS
GIE/GIEH PSPIF(1) PSPIE(1) PSPIP
(1)
0000 000x 0000 000u 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 1111 1111 1111 1111 xxxx xxxx uuuu uuuu
PORTC Data Direction Register Synchronous Serial Port Receive Buffer/Transmit Register WCOL -- SMP SSPOV CKE SSPEN D/A CKP P SSPM3 S SSPM2 R/W SSPM1 UA SSPM0 BF PORTA Data Direction Register
0000 0000 0000 0000 --11 1111 --11 1111 0000 0000 0000 0000
Legend: x = unknown, u = unchanged, - = unimplemented read as '0'. Shaded cells are not used by the MSSP in SPI mode. Note 1: The PSPIF, PSPIE and PSPIP bits are reserved on 28-pin devices. Always maintain these bits clear.
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PIC16F87XA
9.4 I2C Mode
9.4.1 REGISTERS
The MSSP module in I 2C mode fully implements all master and slave functions (including general call support) and provides interrupts on START and STOP bits in hardware to determine a free bus (multi-master function). The MSSP module implements the standard mode specifications, as well as 7-bit and 10-bit addressing. Two pins are used for data transfer: * Serial clock (SCL) - RC3/SCK/SCL * Serial data (SDA) - RC4/SDI/SDA The user must configure these pins as inputs or outputs through the TRISC<4:3> bits. The MSSP module has six registers for I2C operation. These are: MSSP Control Register (SSPCON) MSSP Control Register 2 (SSPCON2) MSSP Status Register (SSPSTAT) Serial Receive/Transmit Buffer (SSPBUF) MSSP Shift Register (SSPSR) - Not directly accessible * MSSP Address Register (SSPADD) SSPCON, SSPCON2 and SSPSTAT are the control and status registers in I2C mode operation. The SSPCON and SSPCON2 registers are readable and writable. The lower 6 bits of the SSPSTAT are read only. The upper two bits of the SSPSTAT are read/ write. SSPSR is the shift register used for shifting data in or out. SSPBUF is the buffer register to which data bytes are written to or read from. SSPADD register holds the slave device address when the SSP is configured in I2C Slave mode. When the SSP is configured in Master mode, the lower seven bits of SSPADD act as the baud rate generator reload value. In receive operations, SSPSR and SSPBUF together create a double buffered receiver. When SSPSR receives a complete byte, it is transferred to SSPBUF and the SSPIF interrupt is set.
Addr Match
* * * * *
FIGURE 9-7:
MSSP BLOCK DIAGRAM (I2C MODE)
Internal Data Bus Read SSPBUF reg Shift Clock SSPSR reg Write
RC3/SCK/SCL
RC4/ SDI/ SDA
MSb
LSb
Match Detect
SSPADD reg START and STOP bit Detect Set, Reset S, P bits (SSPSTAT reg)
During transmission, the SSPBUF is not double buffered. A write to SSPBUF will write to both SSPBUF and SSPSR.
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PIC16F87XA
REGISTER 9-3: SSPSTAT: MSSP STATUS REGISTER (I2C MODE) (ADDRESS 94h)
R/W-0 SMP bit 7 bit 7 SMP: Slew Rate Control bit In Master or Slave mode: 1= Slew rate control disabled for standard speed mode (100 kHz and 1 MHz) 0= Slew rate control enabled for high speed mode (400 kHz) CKE: SMBus Select bit In Master or Slave mode: 1 = Enable SMBus specific inputs 0 = Disable SMBus specific inputs D/A: Data/Address bit In Master mode: Reserved In Slave mode: 1 = Indicates that the last byte received or transmitted was data 0 = Indicates that the last byte received or transmitted was address P: STOP bit 1 = Indicates that a STOP bit has been detected last 0 = STOP bit was not detected last Note: This bit is cleared on RESET and when SSPEN is cleared. S: START bit 1 = Indicates that a START bit has been detected last 0 = START bit was not detected last Note: This bit is cleared on RESET and when SSPEN is cleared. R/W: Read/Write bit information (I2C mode only) In Slave mode: 1 = Read 0 = Write Note: This bit holds the R/W bit information following the last address match. This bit is only valid from the address match to the next START bit, STOP bit, or not ACK bit. In Master mode: 1 = Transmit is in progress 0 = Transmit is not in progress Note: ORing this bit with SEN, RSEN, PEN, RCEN, or ACKEN will indicate if the MSSP is in IDLE mode. UA: Update Address (10-bit Slave mode only) 1 = Indicates that the user needs to update the address in the SSPADD register 0 = Address does not need to be updated BF: Buffer Full Status bit In Transmit mode: 1 = Receive complete, SSPBUF is full 0 = Receive not complete, SSPBUF is empty In Receive mode: 1 = Data Transmit in progress (does not include the ACK and STOP bits), SSPBUF is full 0 = Data Transmit complete (does not include the ACK and STOP bits), SSPBUF is empty Legend: R = Readable bit - n = Value at POR W = Writable bit '1' = Bit is set U = Unimplemented bit, read as `0' '0' = Bit is cleared x = Bit is unknown R/W-0 CKE R-0 D/A R-0 P R-0 S R-0 R/W R-0 UA R-0 BF bit 0
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
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PIC16F87XA
REGISTER 9-4: SSPCON: MSSP CONTROL REGISTER1 (I2C MODE) (ADDRESS 14h)
R/W-0 WCOL bit 7 bit 7 R/W-0 SSPOV R/W-0 SSPEN R/W-0 CKP R/W-0 SSPM3 R/W-0 SSPM2 R/W-0 SSPM1 R/W-0 SSPM0 bit 0
WCOL: Write Collision Detect bit In Master Transmit mode: 1 = A write to the SSPBUF register was attempted while the I2C conditions were not valid for a transmission to be started. (Must be cleared in software.) 0 = No collision In Slave Transmit mode: 1 = The SSPBUF register is written while it is still transmitting the previous word. (Must be cleared in software.) 0 = No collision In Receive mode (Master or Slave modes): This is a "don't care" bit. SSPOV: Receive Overflow Indicator bit In Receive mode: 1 =A byte is received while the SSPBUF register is still holding the previous byte. (Must be cleared in software.) 0 = No overflow In Transmit mode: This is a "don't care" bit in Transmit mode. SSPEN: Synchronous Serial Port Enable bit 1 = Enables the serial port and configures the SDA and SCL pins as the serial port pins 0 = Disables serial port and configures these pins as I/O port pins Note: When enabled, the SDA and SCL pins must be properly configured as input or output. CKP: SCK Release Control bit In Slave mode: 1 = Release clock 0 = Holds clock low (clock stretch). (Used to ensure data setup time.) In Master mode: Unused in this mode SSPM3:SSPM0: Synchronous Serial Port Mode Select bits 1111 = I2C Slave mode, 10-bit address with START and STOP bit interrupts enabled 1110 = I2C Slave mode, 7-bit address with START and STOP bit interrupts enabled 1011 = I2C Firmware Controlled Master mode (Slave IDLE) 1000 = I2C Master mode, clock = FOSC / (4 * (SSPADD+1)) 0111 = I2C Slave mode, 10-bit address 0110 = I2C Slave mode, 7-bit address Note: Bit combinations not specifically listed here are either reserved, or implemented in SPI mode only.
bit 6
bit 5
bit 4
bit 3-0
Legend: R = Readable bit - n = Value at POR W = Writable bit '1' = Bit is set U = Unimplemented bit, read as `0' '0' = Bit is cleared x = Bit is unknown
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PIC16F87XA
REGISTER 9-5: SSPCON2: MSSP CONTROL REGISTER2 (I2C MODE) (ADDRESS 91h)
R/W-0 GCEN bit 7 bit 7 GCEN: General Call Enable bit (Slave mode only) 1 = Enable interrupt when a general call address (0000h) is received in the SSPSR 0 = General call address disabled ACKSTAT: Acknowledge Status bit (Master Transmit mode only) 1 = Acknowledge was not received from slave 0 = Acknowledge was received from slave ACKDT: Acknowledge Data bit (Master Receive mode only) 1 = Not Acknowledge 0 = Acknowledge Note: bit 4 Value that will be transmitted when the user initiates an Acknowledge sequence at the end of a receive. R/W-0 ACKSTAT R/W-0 ACKDT R/W-0 ACKEN R/W-0 RCEN R/W-0 PEN R/W-0 RSEN R/W-0 SEN bit 0
bit 6
bit 5
ACKEN: Acknowledge Sequence Enable bit (Master Receive mode only) 1 = Initiate Acknowledge sequence on SDA and SCL pins, and transmit ACKDT data bit. Automatically cleared by hardware. 0 = Acknowledge sequence IDLE RCEN: Receive Enable bit (Master mode only) 1 = Enables Receive mode for I2C 0 = Receive IDLE PEN: STOP Condition Enable bit (Master mode only) 1 = Initiate STOP condition on SDA and SCL pins. Automatically cleared by hardware. 0 = STOP condition IDLE
bit 3
bit 2
bit 1
RSEN: Repeated START Condition Enabled bit (Master mode only) 1 = Initiate Repeated START condition on SDA and SCL pins. Automatically cleared by hardware. 0 = Repeated START condition IDLE SEN: START Condition Enabled/Stretch Enabled bit In Master mode: 1 = Initiate START condition on SDA and SCL pins. Automatically cleared by hardware. 0 = START condition IDLE In Slave mode: 1 = Clock stretching is enabled for both Slave Transmit and Slave Receive (stretch enabled) 0 = Clock stretching is enabled for Slave Transmit only (PIC16F87X compatibility) Note: For bits ACKEN, RCEN, PEN, RSEN, SEN: If the I2C module is not in the IDLE mode, this bit may not be set (no spooling) and the SSPBUF may not be written (or writes to the SSPBUF are disabled).
bit 0
Legend: R = Readable bit - n = Value at POR reset W = Writable bit '1' = Bit is set U = Unimplemented bit, read as `0' '0' = Bit is cleared x = Bit is unknown
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PIC16F87XA
9.4.2 OPERATION 9.4.3.1 Addressing
The MSSP module functions are enabled by setting MSSP Enable bit, SSPEN (SSPCON<5>). The SSPCON register allows control of the I 2C operation. Four mode selection bits (SSPCON<3:0>) allow one of the following I 2C modes to be selected: * * * * I2C Master mode, clock = OSC/4 (SSPADD +1) I 2C Slave mode (7-bit address) I 2C Slave mode (10-bit address) I 2C Slave mode (7-bit address), with START and STOP bit interrupts enabled * I 2C Slave mode (10-bit address), with START and STOP bit interrupts enabled * I 2C Firmware controlled master operation, slave is IDLE Once the MSSP module has been enabled, it waits for a START condition to occur. Following the START condition, the 8-bits are shifted into the SSPSR register. All incoming bits are sampled with the rising edge of the clock (SCL) line. The value of register SSPSR<7:1> is compared to the value of the SSPADD register. The address is compared on the falling edge of the eighth clock (SCL) pulse. If the addresses match, and the BF and SSPOV bits are clear, the following events occur: 1. 2. 3. 4. The SSPSR register value is loaded into the SSPBUF register. The buffer full bit BF is set. An ACK pulse is generated. MSSP interrupt flag bit SSPIF (PIR1<3>) is set (interrupt is generated if enabled) on the falling edge of the ninth SCL pulse.
Selection of any I 2C mode, with the SSPEN bit set, forces the SCL and SDA pins to be open drain, provided these pins are programmed to inputs by setting the appropriate TRISC bits. To guarantee proper operation of the module, pull-up resistors must be provided externally to the SCL and SDA pins.
9.4.3
SLAVE MODE
In Slave mode, the SCL and SDA pins must be configured as inputs (TRISC<4:3> set). The MSSP module will override the input state with the output data when required (slave-transmitter). Slave mode hardware will always generate an The I interrupt on an address match. Through the mode select bits, the user can also choose to interrupt on START and STOP bits When an address is matched or the data transfer after an address match is received, the hardware automatically will generate the Acknowledge (ACK) pulse and load the SSPBUF register with the received value currently in the SSPSR register. Any combination of the following conditions will cause the MSSP module not to give this ACK pulse: * The buffer full bit, BF (SSPSTAT<0>), was set before the transfer was received. * The overflow bit, SSPOV (SSPCON<6>), was set before the transfer was received. In this case, the SSPSR register value is not loaded into the SSPBUF, but bit SSPIF (PIR1<3>) is set. The BF bit is cleared by reading the SSPBUF register, while bit SSPOV is cleared through software. The SCL clock input must have a minimum high and low for proper operation. The high and low times of the I2C specification, as well as the requirement of the MSSP module, is shown in timing parameter #100 and parameter #101.
2C
In 10-bit Address mode, two address bytes need to be received by the slave. The five Most Significant bits (MSbs) of the first address byte specify if this is a 10-bit address. Bit R/W (SSPSTAT<2>) must specify a write so the slave device will receive the second address byte. For a 10-bit address, the first byte would equal `11110 A9 A8 0', where `A9' and `A8' are the two MSbs of the address. The sequence of events for 10-bit address is as follows, with steps 7 through 9 for the slave-transmitter: 1. 2. Receive first (high) byte of Address (bits SSPIF, BF and bit UA (SSPSTAT<1>) are set). Update the SSPADD register with second (low) byte of Address (clears bit UA and releases the SCL line). Read the SSPBUF register (clears bit BF) and clear flag bit SSPIF. Receive second (low) byte of Address (bits SSPIF, BF, and UA are set). Update the SSPADD register with the first (high) byte of Address. If match releases SCL line, this will clear bit UA. Read the SSPBUF register (clears bit BF) and clear flag bit SSPIF. Receive Repeated START condition. Receive first (high) byte of Address (bits SSPIF and BF are set). Read the SSPBUF register (clears bit BF) and clear flag bit SSPIF.
3. 4. 5.
6. 7. 8. 9.
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PIC16F87XA
9.4.3.2 Reception 9.4.3.3 Transmission
When the R/W bit of the address byte is clear and an address match occurs, the R/W bit of the SSPSTAT register is cleared. The received address is loaded into the SSPBUF register and the SDA line is held low (ACK). When the address byte overflow condition exists, then the No Acknowledge (ACK) pulse is given. An overflow condition is defined as either bit BF (SSPSTAT<0>) is set or bit SSPOV (SSPCON<6>) is set. An MSSP interrupt is generated for each data transfer byte. Flag bit SSPIF (PIR1<3>) must be cleared in software. The SSPSTAT register is used to determine the status of the byte. If SEN is enabled (SSPCON<0>=1), RC3/SCK/SCL will be held low (clock stretch) following each data transfer. The clock must be released by setting bit CKP (SSPCON<4>). See Section 9.4.4 ("Clock Stretching") for more detail. When the R/W bit of the incoming address byte is set and an address match occurs, the R/W bit of the SSPSTAT register is set. The received address is loaded into the SSPBUF register. The ACK pulse will be sent on the ninth bit and pin RC3/SCK/SCL is held low, regardless of SEN (see "Clock Stretching", Section 9.4.4, for more detail). By stretching the clock, the master will be unable to assert another clock pulse until the slave is done preparing the transmit data.The transmit data must be loaded into the SSPBUF register, which also loads the SSPSR register. Then pin RC3/ SCK/SCL should be enabled by setting bit CKP (SSPCON<4>). The eight data bits are shifted out on the falling edge of the SCL input. This ensures that the SDA signal is valid during the SCL high time (Figure 9-9). The ACK pulse from the master-receiver is latched on the rising edge of the ninth SCL input pulse. If the SDA line is high (not ACK), then the data transfer is complete. In this case, when the ACK is latched by the slave, the slave logic is reset (resets SSPSTAT register) and the slave monitors for another occurrence of the START bit. If the SDA line was low (ACK), the next transmit data must be loaded into the SSPBUF register. Again, pin RC3/SCK/SCL must be enabled by setting bit CKP. An MSSP interrupt is generated for each data transfer byte. The SSPIF bit must be cleared in software and the SSPSTAT register is used to determine the status of the byte. The SSPIF bit is set on the falling edge of the ninth clock pulse.
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Advance Information
DS39582A-page 83
FIGURE 9-8:
DS39582A-page 84
Receiving Address A5 A4 A3 A2 A1 ACK D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 R/W = 0 Receiving Data ACK Receiving Data D1 D0 ACK 3 4 5 6 7 8 9 1 2 3 4 5 6 7 8 9 1 2 3 4 5 6 7 8 9 P Bus Master terminates transfer Cleared in software SSPBUF is read SSPOV is set because SSPBUF is still full. ACK is not sent.
PIC16F87XA
SDA
A7
A6
SCL
S
1
2
SSPIF
(PIR1<3>)
I2C SLAVE MODE TIMING WITH SEN = 0 (RECEPTION, 7-BIT ADDRESS)
Advance Information
BF (SSPSTAT<0>)
SSPOV (SSPCON<6>)
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CKP
(CKP does not reset to `0' when SEN = 0)
FIGURE 9-9:
2001 Microchip Technology Inc.
R/W = 1 ACK D1 D0 D4 D3 D5 D7 D6 A1 D3 D2 ACK D5 D4 D7 D6 D2 Transmitting Data Transmitting Data D1 D0 ACK A4 A2 A3 4 SCL held low while CPU responds to SSPIF 5 6 7 8 9 1 2 3 4 5 6 7 8 9 1 2 3 4 5 6 7 8 9 P Cleared in software From SSPIF ISR SSPBUF is written in software SSPBUF is written in software Cleared in software From SSPIF ISR CKP is set in software CKP is set in software
Receiving Address
SDA
A7
A6
A5
SCL
1
2
3
S
Data in sampled
SSPIF (PIR1<3>)
I2C SLAVE MODE TIMING (TRANSMISSION, 7-BIT ADDRESS)
Advance Information
BF (SSPSTAT<0>)
CKP
PIC16F87XA
DS39582A-page 85
FIGURE 9-10:
DS39582A-page 86
Clock is held low until update of SSPADD has taken place R/W = 0 ACK A7 D3 D2 A6 A5 A4 A3 A2 A1 D7 D6 D5 D4 D3 D2 D1 D0 ACK D7 D6 D5 D4 A0 ACK Receive Second Byte of Address Receive Data Byte Receive Data Byte D1 D0 ACK Clock is held low until update of SSPADD has taken place 0 A9 A8 5 1 2 3 4 5 6 7 8 9 1 2 3 4 5 6 7 8 9 1 2 3 4 5 6 7 8 9 6 7 8 9 P Bus Master terminates transfer Cleared in software Cleared in software Cleared in software Dummy read of SSPBUF to clear BF flag SSPOV is set because SSPBUF is still full. ACK is not sent. Cleared by hardware when SSPADD is updated with low byte of address. UA is set indicating that SSPADD needs to be updated Cleared by hardware when SSPADD is updated with high byte of address.
Receive First Byte of Address
PIC16F87XA
SDA
1
1
1
1
SCL
S
1
2
3
4
SSPIF
(PIR1<3>)
Cleared in software
BF (SSPSTAT<0>)
SSPBUF is written with contents of SSPSR
I2C SLAVE MODE TIMING WITH SEN = 0 (RECEPTION, 10-BIT ADDRESS)
Advance Information
SSPOV (SSPCON<6>)
UA (SSPSTAT<1>)
UA is set indicating that the SSPADD needs to be updated
2001 Microchip Technology Inc.
CKP
(CKP does not reset to `0' when SEN = 0)
FIGURE 9-11:
Bus Master terminates transfer Clock is held low until CKP is set to `1' R/W=1 ACK Transmitting Data Byte D7 D6 D5 D4 D3 D2 D1 D0 ACK
2001 Microchip Technology Inc.
Clock is held low until update of SSPADD has taken place R/W = 0 Receive Second Byte of Address Receive First Byte of Address ACK 1 1 1 1 0 A9 A8 ACK A7 A6 A5 A4 A3 A2 A1 A0 1 0 A9 A8 Clock is held low until update of SSPADD has taken place 4 Sr 5 6 7 8 9 1 2 3 4 5 6 7 8 9 1 2 3 4 5 6 7 8 9 1 2 3 4 5 6 7 8 9 P Cleared in software Cleared in software Cleared in software Dummy read of SSPBUF to clear BF flag Dummy read of SSPBUF to clear BF flag Write of SSPBUF BF flag is clear initiates transmit at the end of the third address sequence Completion of data transmission clears BF flag Cleared by hardware when SSPADD is updated with low byte of address. UA is set indicating that SSPADD needs to be updated Cleared by hardware when SSPADD is updated with high byte of address. CKP is set in software CKP is automatically cleared in hardware holding SCL low
Receive First Byte of Address
SDA
1
1
1
SCL
S
1
2
3
SSPIF
(PIR1<3>)
BF (SSPSTAT<0>)
SSPBUF is written with contents of SSPSR
I2C SLAVE MODE TIMING (TRANSMISSION, 10-BIT ADDRESS)
Advance Information
UA (SSPSTAT<1>)
UA is set indicating that the SSPADD needs to be updated
CKP (SSPCON<4>)
PIC16F87XA
DS39582A-page 87
PIC16F87XA
9.4.4 CLOCK STRETCHING 9.4.4.3
Both 7 and 10-bit Slave modes implement automatic clock stretching during a transmit sequence. The SEN bit (SSPCON2<0>) allows clock stretching to be enabled during receives. Setting SEN will cause the SCL pin to be held low at the end of each data receive sequence.
Clock Stretching for 7-bit Slave Transmit Mode
7-bit Slave Transmit mode implements clock stretching by clearing the CKP bit after the falling edge of the ninth clock, if the BF bit is clear. This occurs regardless of the state of the SEN bit. The user's ISR must set the CKP bit before transmission is allowed to continue. By holding the SCL line low, the user has time to service the ISR and load the contents of the SSPBUF before the master device can initiate another transmit sequence (see Figure 9-9). Note 1: If the user loads the contents of SSPBUF, setting the BF bit before the falling edge of the ninth clock, the CKP bit will not be cleared and clock stretching will not occur. 2: The CKP bit can be set in software regardless of the state of the BF bit.
9.4.4.1
Clock Stretching for 7-bit Slave Receive Mode (SEN = 1)
In 7-bit Slave Receive mode, on the falling edge of the ninth clock at the end of the ACK sequence, if the BF bit is set, the CKP bit in the SSPCON register is automatically cleared, forcing the SCL output to be held low. The CKP being cleared to `0' will assert the SCL line low. The CKP bit must be set in the user's ISR before reception is allowed to continue. By holding the SCL line low, the user has time to service the ISR and read the contents of the SSPBUF before the master device can initiate another receive sequence. This will prevent buffer overruns from occurring (see Figure 9-13). Note 1: If the user reads the contents of the SSPBUF before the falling edge of the ninth clock, thus clearing the BF bit, the CKP bit will not be cleared and clock stretching will not occur. 2: The CKP bit can be set in software, regardless of the state of the BF bit. The user should be careful to clear the BF bit in the ISR before the next receive sequence in order to prevent an overflow condition.
9.4.4.4
Clock Stretching for 10-bit Slave Transmit Mode
In 10-bit Slave Transmit mode, clock stretching is controlled during the first two address sequences by the state of the UA bit, just as it is in 10-bit Slave Receive mode. The first two addresses are followed by a third address sequence, which contains the high order bits of the 10-bit address and the R/W bit set to `1'. After the third address sequence is performed, the UA bit is not set, the module is now configured in Transmit mode, and clock stretching is controlled by the BF flag as in 7-bit Slave Transmit mode (see Figure 9-11).
9.4.4.2
Clock Stretching for 10-bit Slave Receive Mode (SEN = 1)
In 10-bit Slave Receive mode, during the address sequence, clock stretching automatically takes place but CKP is not cleared. During this time, if the UA bit is set after the ninth clock, clock stretching is initiated. The UA bit is set after receiving the upper byte of the 10-bit address, and following the receive of the second byte of the 10-bit address, with the R/W bit cleared to `0'. The release of the clock line occurs upon updating SSPADD. Clock stretching will occur on each data receive sequence as described in 7-bit mode. Note: If the user polls the UA bit and clears it by updating the SSPADD register before the falling edge of the ninth clock occurs, and if the user hasn't cleared the BF bit by reading the SSPBUF register before that time, then the CKP bit will still NOT be asserted low. Clock stretching on the basis of the state of the BF bit only occurs during a data sequence, not an address sequence.
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9.4.4.5 Clock Synchronization and the CKP Bit
When the CKP bit is cleared, the SCL output is forced to `0'; however, setting the CKP bit will not assert the SCL output low until the SCL output is already sampled low. Therefore, the CKP bit will not assert the SCL line until an external I2C master device has already asserted the SCL line. The SCL output will remain low until the CKP bit is set, and all other devices on the I2C bus have de-asserted SCL. This ensures that a write to the CKP bit will not violate the minimum high time requirement for SCL (see Figure 9-12).
FIGURE 9-12:
CLOCK SYNCHRONIZATION TIMING
Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4
SDA
DX
DX-1
SCL
CKP
Master device asserts clock Master device de-asserts clock
WR SSPCON
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FIGURE 9-13:
DS39582A-page 90
Clock is not held low because buffer full bit is clear prior to falling edge of 9th clock Clock is held low until CKP is set to `1' ACK Receiving Data D7 D6 D5 D4 D3 D2 D1 D0 D2 D1 D0 Receiving Address A5 A4 A3 A2 A1 ACK D7 D6 D5 D4 D3 R/W = 0 Receiving Data Clock is not held low because ACK = 1 ACK 3 4 5 6 7 8 9 1 2 3 4 5 6 7 8 9 1 2 3 4 5 6 7 8 9 P Bus Master terminates transfer Cleared in software SSPBUF is read SSPOV is set because SSPBUF is still full. ACK is not sent.
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SDA
A7
A6
SCL
S
1
2
SSPIF
(PIR1<3>)
I2C SLAVE MODE TIMING WITH SEN = 1 (RECEPTION, 7-BIT ADDRESS)
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If BF is cleared prior to the falling edge of the 9th clock, CKP will not be reset to `0' and no clock stretching will occur. BF is set after falling edge of the 9th clock, CKP is reset to `0' and clock stretching occurs CKP written to `1' in software
BF (SSPSTAT<0>)
SSPOV (SSPCON<6>)
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CKP
FIGURE 9-14:
Clock is held low until update of SSPADD has taken place Clock is held low until CKP is set to `1' Receive Data Byte D1 D0 D7 D6 D5 D4 ACK D3 D2 R/W = 0 ACK A7 A6 A5 A4 A3 A2 A1 A0 ACK D7 D6 D5 D4 D3 D2 Receive Second Byte of Address Receive Data Byte
Clock is held low until update of SSPADD has taken place
Clock is not held low because ACK = 1 ACK D1 D0
Receive First Byte of Address A9 A8
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6 1 2 7 8 9 1 2 3 4 5 6 7 8 9 1 2 3 4 5 6 7 8 9 3 4 5 6 7 8 9 P Cleared in software Cleared in software Cleared in software Bus Master terminates transfer Dummy read of SSPBUF to clear BF flag Dummy read of SSPBUF to clear BF flag SSPOV is set because SSPBUF is still full. ACK is not sent. Cleared by hardware when SSPADD is updated with low byte of address after falling edge of ninth clock. UA is set indicating that SSPADD needs to be updated Note: Cleared by hardware when SSPADD is updated with high byte of address after falling edge of ninth clock. An update of the SSPADD register before the falling edge of the ninth clock will have no effect on UA, and UA will remain set. Note: An update of the SSPADD register before the falling edge of the ninth clock will have no effect on UA, and UA will remain set. CKP written to `1' in software
SDA
1
1
1
1
0
SCL
S
1
2
3
4
5
SSPIF
(PIR1<3>)
Cleared in software
BF (SSPSTAT<0>)
SSPBUF is written with contents of SSPSR
SSPOV (SSPCON<6>)
I2C SLAVE MODE TIMING SEN = 1 (RECEPTION, 10-BIT ADDRESS)
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UA (SSPSTAT<1>)
UA is set indicating that the SSPADD needs to be updated
CKP
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9.4.5 GENERAL CALL ADDRESS SUPPORT
The addressing procedure for the I2C bus is such that the first byte after the START condition usually determines which device will be the slave addressed by the master. The exception is the general call address, which can address all devices. When this address is used, all devices should, in theory, respond with an Acknowledge. The general call address is one of eight addresses reserved for specific purposes by the I2C protocol. It consists of all 0's with R/W = 0. The general call address is recognized when the General Call Enable bit (GCEN) is enabled (SSPCON2<7> set). Following a START bit detect, 8-bits are shifted into the SSPSR and the address is compared against the SSPADD. It is also compared to the general call address and fixed in hardware. If the general call address matches, the SSPSR is transferred to the SSPBUF, the BF flag bit is set (eighth bit), and on the falling edge of the ninth bit (ACK bit), the SSPIF interrupt flag bit is set. When the interrupt is serviced, the source for the interrupt can be checked by reading the contents of the SSPBUF. The value can be used to determine if the address was device specific or a general call address. In 10-bit mode, the SSPADD is required to be updated for the second half of the address to match, and the UA bit is set (SSPSTAT<1>). If the general call address is sampled when the GCEN bit is set, while the slave is configured in 10-bit Address mode, then the second half of the address is not necessary, the UA bit will not be set, and the slave will begin receiving data after the Acknowledge (Figure 9-15).
FIGURE 9-15:
SLAVE MODE GENERAL CALL ADDRESS SEQUENCE (7 OR 10-BIT ADDRESS MODE)
Address is compared to General Call Address after ACK, set interrupt R/W = 0 ACK D7 Receiving data D6 D5 D4 D3 D2 D1 D0 ACK
SDA SCL S SSPIF BF (SSPSTAT<0>) 1
General Call Address
2
3
4
5
6
7
8
9
1
2
3
4
5
6
7
8
9
Cleared in software SSPBUF is read SSPOV (SSPCON<6>) '0'
GCEN (SSPCON2<7>)
'1'
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9.4.6 MASTER MODE
Note: Master mode is enabled by setting and clearing the appropriate SSPM bits in SSPCON and by setting the SSPEN bit. In Master mode, the SCL and SDA lines are manipulated by the MSSP hardware. Master mode of operation is supported by interrupt generation on the detection of the START and STOP conditions. The STOP (P) and START (S) bits are cleared from a RESET, or when the MSSP module is disabled. Control of the I 2C bus may be taken when the P bit is set or the bus is IDLE, with both the S and P bits clear. In Firmware Controlled Master mode, user code conducts all I 2C bus operations based on START and STOP bit conditions. Once Master mode is enabled, the user has six options. 1. 2. 3. 4. 5. 6. Assert a START condition on SDA and SCL. Assert a Repeated START condition on SDA and SCL. Write to the SSPBUF register, initiating transmission of data/address. Configure the I2C port to receive data. Generate an Acknowledge condition at the end of a received byte of data. Generate a STOP Condition on SDA and SCL. The MSSP module, when configured in I2C Master mode, does not allow queueing of events. For instance, the user is not allowed to initiate a START condition and immediately write the SSPBUF register to initiate transmission before the START condition is complete. In this case, the SSPBUF will not be written to and the WCOL bit will be set, indicating that a write to the SSPBUF did not occur.
The following events will cause SSP Interrupt Flag bit, SSPIF, to be set (SSP Interrupt if enabled): * * * * * START condition STOP condition Data transfer byte transmitted/received Acknowledge Transmit Repeated START
FIGURE 9-16:
MSSP BLOCK DIAGRAM (I2C MASTER MODE)
Internal Data Bus Read SSPBUF Write Baud Rate Generator Clock Arbitrate/WCOL Detect (hold off clock source) DS39582A-page 93 Shift Clock SSPSR Receive Enable MSb LSb SSPM3:SSPM0 SSPADD<6:0>
SDA SDA In
SCL
SCL In Bus Collision
START bit Detect STOP bit Detect Write Collision Detect Clock Arbitration State Counter for end of XMIT/RCV
Set/Reset, S, P, WCOL (SSPSTAT) Set SSPIF, BCLIF Reset ACKSTAT, PEN (SSPCON2)
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Clock Cntl
Start bit, Stop bit, Acknowledge Generate
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9.4.6.1 I2C Master Mode Operation
A typical transmit sequence would go as follows: 1. The user generates a START Condition by setting the START enable bit, SEN (SSPCON2<0>). 2. SSPIF is set. The MSSP module will wait the required START time before any other operation takes place. 3. The user loads the SSPBUF with the slave address to transmit. 4. Address is shifted out the SDA pin until all 8 bits are transmitted. 5. The MSSP Module shifts in the ACK bit from the slave device and writes its value into the SSPCON2 register (SSPCON2<6>). 6. The MSSP module generates an interrupt at the end of the ninth clock cycle by setting the SSPIF bit. 7. The user loads the SSPBUF with eight bits of data. 8. Data is shifted out the SDA pin until all 8 bits are transmitted. 9. The MSSP Module shifts in the ACK bit from the slave device and writes its value into the SSPCON2 register (SSPCON2<6>). 10. The MSSP module generates an interrupt at the end of the ninth clock cycle by setting the SSPIF bit. 11. The user generates a STOP condition by setting the STOP enable bit, PEN (SSPCON2<2>). 12. Interrupt is generated once the STOP condition is complete. The master device generates all of the serial clock pulses and the START and STOP conditions. A transfer is ended with a STOP condition or with a repeated START condition. Since the repeated START condition is also the beginning of the next serial transfer, the I2C bus will not be released. In Master Transmitter mode, serial data is output through SDA, while SCL outputs the serial clock. The first byte transmitted contains the slave address of the receiving device (7 bits) and the Read/Write (R/W) bit. In this case, the R/W bit will be logic '0'. Serial data is transmitted 8 bits at a time. After each byte is transmitted, an Acknowledge bit is received. START and STOP conditions are output to indicate the beginning and the end of a serial transfer. In Master Receive mode, the first byte transmitted contains the slave address of the transmitting device (7 bits) and the R/W bit. In this case, the R/W bit will be logic '1'. Thus, the first byte transmitted is a 7-bit slave address followed by a '1' to indicate receive bit. Serial data is received via SDA, while SCL outputs the serial clock. Serial data is received 8 bits at a time. After each byte is received, an Acknowledge bit is transmitted. START and STOP conditions indicate the beginning and end of transmission. The baud rate generator used for the SPI mode operation is used to set the SCL clock frequency for either 100 kHz, 400 kHz or 1 MHz I2C operation. See Section 9.4.7 ("Baud Rate Generator") for more detail.
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9.4.7
I2C
BAUD RATE GENERATOR
In Master mode, the baud rate generator (BRG) reload value is placed in the lower 7 bits of the SSPADD register (Figure 9-17). When a write occurs to SSPBUF, the baud rate generator will automatically begin counting. The BRG counts down to 0 and stops until another reload has taken place. The BRG count is decremented twice per instruction cycle (TCY) on the Q2 and Q4 clocks. In I2C Master mode, the BRG is reloaded automatically.
Once the given operation is complete, (i.e. transmission of the last data bit is followed by ACK), the internal clock will automatically stop counting and the SCL pin will remain in its last state. Table 15-3 demonstrates clock rates based on instruction cycles and the BRG value loaded into SSPADD.
FIGURE 9-17:
BAUD RATE GENERATOR BLOCK DIAGRAM
SSPM3:SSPM0 SSPADD<6:0>
SSPM3:SSPM0 SCL
Reload Control CLKOUT
Reload
BRG Down Counter
FOSC/4
TABLE 9-3:
FCY
I2C CLOCK RATE W/BRG
FCY*2 20 MHz 20 MHz 20 MHz 8 MHz 8 MHz 8 MHz 2 MHz 2 MHz 2 MHz I2C BRG VALUE 19h 20h 3Fh 0Ah 0Dh 28h 03h 0Ah 00h FSCL (2 rollovers of BRG) 400 kHz(1) 312.5 kHz 100 kHz 400 kHz(1) 308 kHz 100 kHz 333 kHz(1) 100 kHz 1 MHz(1)
10 MHz 10 MHz 10 MHz 4 MHz 4 MHz 4 MHz 1 MHz 1 MHz 1 MHz I2C
Note 1: The interface does not conform to the 400 kHz specification (which applies to rates greater than 100 kHz) in all details, but may be used with care where higher rates are required by the application.
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9.4.7.1 Clock Arbitration
Clock arbitration occurs when the master, during any receive, transmit or Repeated START/STOP condition, de-asserts the SCL pin (SCL allowed to float high). When the SCL pin is allowed to float high, the baud rate generator (BRG) is suspended from counting until the SCL pin is actually sampled high. When the SCL pin is sampled high, the baud rate generator is reloaded with the contents of SSPADD<6:0> and begins counting. This ensures that the SCL high time will always be at least one BRG rollover count, in the event that the clock is held low by an external device (Figure 15-18).
FIGURE 9-18:
SDA
BAUD RATE GENERATOR TIMING WITH CLOCK ARBITRATION
DX DX-1 SCL allowed to transition high
SCL de-asserted but slave holds SCL low (clock arbitration) SCL BRG decrements on Q2 and Q4 cycles BRG Value 03h 02h 01h 00h (hold off)
03h
02h
SCL is sampled high, reload takes place and BRG starts its count. BRG Reload
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9.4.8 I2C MASTER MODE START CONDITION TIMING 9.4.8.1 WCOL Status Flag
If the user writes the SSPBUF when a START sequence is in progress, the WCOL is set and the contents of the buffer are unchanged (the write doesn't occur). Note: Because queueing of events is not allowed, writing to the lower 5 bits of SSPCON2 is disabled until the START condition is complete.
To initiate a START condition, the user sets the START condition enable bit, SEN (SSPCON2<0>). If the SDA and SCL pins are sampled high, the baud rate generator is reloaded with the contents of SSPADD<6:0> and starts its count. If SCL and SDA are both sampled high when the baud rate generator times out (TBRG), the SDA pin is driven low. The action of the SDA being driven low, while SCL is high, is the START condition, and causes the S bit (SSPSTAT<3>) to be set. Following this, the baud rate generator is reloaded with the contents of SSPADD<6:0> and resumes its count. When the baud rate generator times out (TBRG), the SEN bit (SSPCON2<0>) will be automatically cleared by hardware, the baud rate generator is suspended, leaving the SDA line held low and the START condition is complete. Note: If, at the beginning of the START condition, the SDA and SCL pins are already sampled low, or if during the START condition, the SCL line is sampled low before the SDA line is driven low, a bus collision occurs, the Bus Collision Interrupt Flag BCLIF is set, the START condition is aborted, and the I2C module is reset into its IDLE state.
FIGURE 9-19:
FIRST START BIT TIMING
Set S bit (SSPSTAT<3>) SDA = 1, SCL = 1 At completion of START bit, Hardware clears SEN bit and sets SSPIF bit TBRG Write to SSPBUF occurs here 1st Bit SDA TBRG 2nd Bit
Write to SEN bit occurs here.
TBRG
SCL S
TBRG
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9.4.9 I2C MASTER MODE REPEATED START CONDITION TIMING
Immediately following the SSPIF bit getting set, the user may write the SSPBUF with the 7-bit address in 7-bit mode, or the default first address in 10-bit mode. After the first eight bits are transmitted and an ACK is received, the user may then transmit an additional eight bits of address (10-bit mode), or eight bits of data (7-bit mode).
A Repeated START condition occurs when the RSEN bit (SSPCON2<1>) is programmed high and the I2C logic module is in the IDLE state. When the RSEN bit is set, the SCL pin is asserted low. When the SCL pin is sampled low, the baud rate generator is loaded with the contents of SSPADD<5:0> and begins counting. The SDA pin is released (brought high) for one baud rate generator count (TBRG). When the baud rate generator times out, if SDA is sampled high, the SCL pin will be de-asserted (brought high). When SCL is sampled high, the baud rate generator is reloaded with the contents of SSPADD<6:0> and begins counting. SDA and SCL must be sampled high for one TBRG. This action is then followed by assertion of the SDA pin (SDA = 0) for one TBRG, while SCL is high. Following this, the RSEN bit (SSPCON2<1>) will be automatically cleared and the baud rate generator will not be reloaded, leaving the SDA pin held low. As soon as a START condition is detected on the SDA and SCL pins, the S bit (SSPSTAT<3>) will be set. The SSPIF bit will not be set until the baud rate generator has timed out. Note 1: If RSEN is programmed while any other event is in progress, it will not take effect. 2: A bus collision during the Repeated START condition occurs if: * SDA is sampled low when SCL goes from low to high. * SCL goes low before SDA is asserted low. This may indicate that another master is attempting to transmit a data "1".
9.4.9.1
WCOL Status Flag
If the user writes the SSPBUF when a Repeated START sequence is in progress, the WCOL is set and the contents of the buffer are unchanged (the write doesn't occur). Note: Because queueing of events is not allowed, writing of the lower 5 bits of SSPCON2 is disabled until the Repeated START condition is complete.
FIGURE 9-20:
REPEAT START CONDITION WAVEFORM
Set S (SSPSTAT<3>) Write to SSPCON2 occurs here. SDA = 1, SCL (no change) SDA = 1, SCL = 1 At completion of START bit, hardware clear RSEN bit and set SSPIF TBRG 1st Bit SDA Falling edge of ninth clock End of Xmit Write to SSPBUF occurs here. TBRG TBRG Sr = Repeated START
TBRG
TBRG
SCL
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9.4.10 I2C MASTER MODE TRANSMISSION 9.4.10.3 ACKSTAT Status Flag
In Transmit mode, the ACKSTAT bit (SSPCON2<6>) is cleared when the slave has sent an Acknowledge (ACK = 0), and is set when the slave does Not Acknowledge (ACK = 1). A slave sends an Acknowledge when it has recognized its address (including a general call), or when the slave has properly received its data.
Transmission of a data byte, a 7-bit address or the other half of a 10-bit address is accomplished by simply writing a value to the SSPBUF register. This action will set the buffer full flag bit, BF, and allow the baud rate generator to begin counting and start the next transmission. Each bit of address/data will be shifted out onto the SDA pin after the falling edge of SCL is asserted (see data hold time specification parameter #106). SCL is held low for one baud rate generator rollover count (TBRG). Data should be valid before SCL is released high (see Data setup time specification parameter #107). When the SCL pin is released high, it is held that way for TBRG. The data on the SDA pin must remain stable for that duration and some hold time after the next falling edge of SCL. After the eighth bit is shifted out (the falling edge of the eighth clock), the BF flag is cleared and the master releases SDA. This allows the slave device being addressed to respond with an ACK bit during the ninth bit time, if an address match occurred or if data was received properly. The status of ACK is written into the ACKDT bit on the falling edge of the ninth clock. If the master receives an Acknowledge, the Acknowledge status bit, ACKSTAT, is cleared. If not, the bit is set. After the ninth clock, the SSPIF bit is set and the master clock (baud rate generator) is suspended until the next data byte is loaded into the SSPBUF, leaving SCL low and SDA unchanged (Figure 9-21). After the write to the SSPBUF, each bit of address will be shifted out on the falling edge of SCL, until all seven address bits and the R/W bit are completed. On the falling edge of the eighth clock, the master will de-assert the SDA pin, allowing the slave to respond with an Acknowledge. On the falling edge of the ninth clock, the master will sample the SDA pin to see if the address was recognized by a slave. The status of the ACK bit is loaded into the ACKSTAT status bit (SSPCON2<6>). Following the falling edge of the ninth clock transmission of the address, the SSPIF is set, the BF flag is cleared and the baud rate generator is turned off until another write to the SSPBUF takes place, holding SCL low and allowing SDA to float.
9.4.11
I2C MASTER MODE RECEPTION
Master mode reception is enabled by programming the receive enable bit, RCEN (SSPCON2<3>). Note: The MSSP Module must be in an IDLE state before the RCEN bit is set, or the RCEN bit will be disregarded.
The baud rate generator begins counting, and on each rollover, the state of the SCL pin changes (high to low/ low to high) and data is shifted into the SSPSR. After the falling edge of the eighth clock, the receive enable flag is automatically cleared, the contents of the SSPSR are loaded into the SSPBUF, the BF flag bit is set, the SSPIF flag bit is set and the baud rate generator is suspended from counting, holding SCL low. The MSSP is now in IDLE state, awaiting the next command. When the buffer is read by the CPU, the BF flag bit is automatically cleared. The user can then send an Acknowledge bit at the end of reception, by setting the Acknowledge sequence enable bit, ACKEN (SSPCON2<4>).
9.4.11.1
BF Status Flag
In receive operation, the BF bit is set when an address or data byte is loaded into SSPBUF from SSPSR. It is cleared when the SSPBUF register is read.
9.4.11.2
SSPOV Status Flag
In receive operation, the SSPOV bit is set when 8 bits are received into the SSPSR and the BF flag bit is already set from a previous reception.
9.4.11.3
WCOL Status Flag
9.4.10.1
BF Status Flag
In Transmit mode, the BF bit (SSPSTAT<0>) is set when the CPU writes to SSPBUF and is cleared when all 8 bits are shifted out.
If the user writes the SSPBUF when a receive is already in progress (i.e., SSPSR is still shifting in a data byte), the WCOL bit is set and the contents of the buffer are unchanged (the write doesn't occur).
9.4.10.2
WCOL Status Flag
If the user writes the SSPBUF when a transmit is already in progress, (i.e., SSPSR is still shifting out a data byte), the WCOL is set and the contents of the buffer are unchanged (the write doesn't occur). WCOL must be cleared in software.
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FIGURE 9-21:
DS39582A-page 100
Write SSPCON2<0> SEN = 1 START condition begins From Slave, clear ACKSTAT bit SSPCON2<6> R/W = 0 A1 ACK = 0 D7 D6 D5 D4 D3 D2 D1 Transmitting Data or Second Half of 10-bit Address D0 ACK SEN = 0 Transmit Address to Slave SDA A7 SSPBUF written with 7-bit address and R/W start transmit SCL S 1 2 3 4 5 6 7 8 9 1 SCL held low while CPU responds to SSPIF 2 3 4 5 6 7 8 9 P A6 A5 A4 A3 A2 ACKSTAT in SSPCON2 = 1 SSPIF Cleared in software Cleared in software service routine From SSP interrupt Cleared in software BF (SSPSTAT<0>) SSPBUF written SEN After START condition SEN cleared by hardware. SSPBUF is written in software PEN
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I 2C MASTER MODE WAVEFORM (TRANSMISSION, 7 OR 10-BIT ADDRESS)
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R/W
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FIGURE 9-22:
Write to SSPCON2<4> to start Acknowledge sequence SDA = ACKDT (SSPCON2<5>) = 0 Master configured as a receiver by programming SSPCON2<3>, (RCEN = 1) ACK from Slave R/W = 1 Receiving Data from Slave ACK Receiving Data from Slave RCEN cleared automatically ACK RCEN = 1 START next receive RCEN cleared automatically ACK from Master SDA = ACKDT = 0 Set ACKEN, start Acknowledge sequence SDA = ACKDT = 1 PEN bit = 1 written here
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A1 D0 D7 D6 D5 D4 D3 D2 D1 D7 D6 D5 D4 D3 D2 D1 D0
ACK ACK is not sent Bus Master terminates transfer
Write to SSPCON2<0> (SEN = 1) Begin START Condition
SEN = 0 Write to SSPBUF occurs here Start XMIT
Transmit Address to Slave
SDA
A7
A6 A5 A4 A3 A2
SCL
S
Set SSPIF interrupt at end of receive
1 5 1 2 3 4 5 1 2 3 4
2
3 4 8 6 7 8 9
6
7 9
5
6
7
8
9
Set SSPIF at end of receive
P
Set SSPIF interrupt at end of Acknowledge sequence
Data shifted in on falling edge of CLK
SSPIF
Cleared in software Cleared in software
Set SSPIF interrupt at end of Acknowledge sequence Cleared in software Cleared in software
I 2C MASTER MODE WAVEFORM (RECEPTION, 7-BIT ADDRESS)
Advance Information
Last bit is shifted into SSPSR and contents are unloaded into SSPBUF
SDA = 0, SCL = 1 while CPU responds to SSPIF
Cleared in software
Set P bit (SSPSTAT<4>) and SSPIF
BF (SSPSTAT<0>)
SSPOV
SSPOV is set because SSPBUF is still full
ACKEN
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9.4.12 ACKNOWLEDGE SEQUENCE TIMING 9.4.13 STOP CONDITION TIMING
An Acknowledge sequence is enabled by setting the Acknowledge sequence enable bit, ACKEN (SSPCON2<4>). When this bit is set, the SCL pin is pulled low and the contents of the Acknowledge data bit is presented on the SDA pin. If the user wishes to generate an Acknowledge, then the ACKDT bit should be cleared. If not, the user should set the ACKDT bit before starting an Acknowledge sequence. The baud rate generator then counts for one rollover period (TBRG) and the SCL pin is de-asserted (pulled high). When the SCL pin is sampled high (clock arbitration), the baud rate generator counts for TBRG. The SCL pin is then pulled low. Following this, the ACKEN bit is automatically cleared, the baud rate generator is turned off and the MSSP module then goes into IDLE mode (Figure 9-23). A STOP bit is asserted on the SDA pin at the end of a receive/transmit, by setting the STOP sequence enable bit, PEN (SSPCON2<2>). At the end of a receive/ transmit, the SCL line is held low after the falling edge of the ninth clock. When the PEN bit is set, the master will assert the SDA line low. When the SDA line is sampled low, the baud rate generator is reloaded and counts down to 0. When the baud rate generator times out, the SCL pin will be brought high, and one TBRG (baud rate generator rollover count) later, the SDA pin will be de-asserted. When the SDA pin is sampled high while SCL is high, the P bit (SSPSTAT<4>) is set. A TBRG later, the PEN bit is cleared and the SSPIF bit is set (Figure 9-24).
9.4.13.1
WCOL Status Flag
9.4.12.1
WCOL Status Flag
If the user writes the SSPBUF when an Acknowledge sequence is in progress, then WCOL is set and the contents of the buffer are unchanged (the write doesn't occur).
If the user writes the SSPBUF when a STOP sequence is in progress, then the WCOL bit is set and the contents of the buffer are unchanged (the write doesn't occur).
FIGURE 9-23:
ACKNOWLEDGE SEQUENCE WAVEFORM
Acknowledge sequence starts here, Write to SSPCON2 ACKEN = 1, ACKDT = 0 TBRG SDA D0 ACK TBRG ACKEN automatically cleared
SCL
8
9
SSPIF
Set SSPIF at the end of receive Note: TBRG = one baud rate generator period.
Cleared in software
Cleared in software Set SSPIF at the end of Acknowledge sequence
FIGURE 9-24:
STOP CONDITION RECEIVE OR TRANSMIT MODE
Write to SSPCON2 Set PEN Falling edge of 9th clock TBRG SCL = 1 for TBRG, followed by SDA = 1 for TBRG after SDA sampled high. P bit (SSPSTAT<4>) is set PEN bit (SSPCON2<2>) is cleared by hardware and the SSPIF bit is set
SCL
SDA
ACK P TBRG TBRG TBRG SCL brought high after TBRG SDA asserted low before rising edge of clock to setup STOP condition.
Note: TBRG = one baud rate generator period.
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9.4.14 SLEEP OPERATION
I2C
9.4.17
While in SLEEP mode, the module can receive addresses or data, and when an address match or complete byte transfer occurs, wake the processor from SLEEP (if the MSSP interrupt is enabled).
MULTI -MASTER COMMUNICATION, BUS COLLISION, AND BUS ARBITRATION
9.4.15
EFFECT OF A RESET
A RESET disables the MSSP module and terminates the current transfer.
9.4.16
MULTI-MASTER MODE
In Multi-Master mode, the interrupt generation on the detection of the START and STOP conditions allows the determination of when the bus is free. The STOP (P) and START (S) bits are cleared from a RESET or when the MSSP module is disabled. Control of the I 2C bus may be taken when the P bit (SSPSTAT<4>) is set, or the bus is IDLE, with both the S and P bits clear. When the bus is busy, enabling the SSP Interrupt will generate the interrupt when the STOP condition occurs. In multi-master operation, the SDA line must be monitored for arbitration, to see if the signal level is at the expected output level. This check is performed in hardware, with the result placed in the BCLIF bit. The states where arbitration can be lost are: * * * * * Address Transfer Data Transfer A START Condition A Repeated START Condition An Acknowledge Condition
Multi-Master mode support is achieved by bus arbitration. When the master outputs address/data bits onto the SDA pin, arbitration takes place when the master outputs a '1' on SDA by letting SDA float high and another master asserts a '0'. When the SCL pin floats high, data should be stable. If the expected data on SDA is a '1' and the data sampled on the SDA pin = '0', then a bus collision has taken place. The master will set the Bus Collision Interrupt Flag, BCLIF, and reset the I2C port to its IDLE state (Figure 9-25). If a transmit was in progress when the bus collision occurred, the transmission is halted, the BF flag is cleared, the SDA and SCL lines are de-asserted, and the SSPBUF can be written to. When the user services the bus collision Interrupt Service Routine, and if the I2C bus is free, the user can resume communication by asserting a START condition. If a START, Repeated START, STOP, or Acknowledge condition was in progress when the bus collision occurred, the condition is aborted, the SDA and SCL lines are de-asserted, and the respective control bits in the SSPCON2 register are cleared. When the user services the bus collision Interrupt Service Routine, and if the I2C bus is free, the user can resume communication by asserting a START condition. The Master will continue to monitor the SDA and SCL pins. If a STOP condition occurs, the SSPIF bit will be set. A write to the SSPBUF will start the transmission of data at the first data bit, regardless of where the transmitter left off when the bus collision occurred. In Multi-Master mode, the interrupt generation on the detection of START and STOP conditions allows the determination of when the bus is free. Control of the I2C bus can be taken when the P bit is set in the SSPSTAT register, or the bus is IDLE and the S and P bits are cleared.
FIGURE 9-25:
BUS COLLISION TIMING FOR TRANSMIT AND ACKNOWLEDGE
Data changes while SCL = 0 SDA line pulled low by another source SDA released by master Sample SDA. While SCL is high data doesn't match what is driven by the master. Bus collision has occurred.
SDA
SCL
Set bus collision interrupt (BCLIF).
BCLIF
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9.4.17.1 Bus Collision During a START Condition
During a START condition, a bus collision occurs if: a) b) SDA or SCL are sampled low at the beginning of the START condition (Figure 9-26). SCL is sampled low before SDA is asserted low (Figure 9-27). If the SDA pin is sampled low during this count, the BRG is reset and the SDA line is asserted early (Figure 9-28). If, however, a '1' is sampled on the SDA pin, the SDA pin is asserted low at the end of the BRG count. The baud rate generator is then reloaded and counts down to 0, and during this time, if the SCL pin is sampled as '0', a bus collision does not occur. At the end of the BRG count, the SCL pin is asserted low. Note: The reason that bus collision is not a factor during a START condition, is that no two bus masters can assert a START condition at the exact same time. Therefore, one master will always assert SDA before the other. This condition does not cause a bus collision, because the two masters must be allowed to arbitrate the first address following the START condition. If the address is the same, arbitration must be allowed to continue into the data portion, Repeated START or STOP conditions.
During a START condition, both the SDA and the SCL pins are monitored. If the SDA pin is already low, or the SCL pin is already low, then all of the following occur: * the START condition is aborted, * the BCLIF flag is set, and * the MSSP module is reset to its IDLE state (Figure 9-26). The START condition begins with the SDA and SCL pins de-asserted. When the SDA pin is sampled high, the baud rate generator is loaded from SSPADD<6:0> and counts down to 0. If the SCL pin is sampled low while SDA is high, a bus collision occurs, because it is assumed that another master is attempting to drive a data '1' during the START condition.
FIGURE 9-26:
BUS COLLISION DURING START CONDITION (SDA ONLY)
SDA goes low before the SEN bit is set. Set BCLIF, S bit and SSPIF set because SDA = 0, SCL = 1
SDA
SCL Set SEN, enable START condition if SDA = 1, SCL=1 SEN SDA sampled low before START condition. Set BCLIF. S bit and SSPIF set because SDA = 0, SCL = 1. SSPIF and BCLIF are cleared in software. S SEN cleared automatically because of bus collision. SSP module reset into IDLE state.
BCLIF
SSPIF
SSPIF and BCLIF are cleared in software.
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FIGURE 9-27: BUS COLLISION DURING START CONDITION (SCL = 0)
SDA = 0, SCL = 1
TBRG TBRG
SDA
Set SEN, enable START sequence if SDA = 1, SCL = 1 SCL = 0 before SDA = 0, bus collision occurs. Set BCLIF. SCL = 0 before BRG time-out, bus collision occurs. Set BCLIF.
SCL SEN
BCLIF
Interrupt cleared in software.
S SSPIF
'0' '0'
'0' '0'
FIGURE 9-28:
BRG RESET DUE TO SDA ARBITRATION DURING START CONDITION
SDA = 0, SCL = 1 Set S Less than TBRG
TBRG
Set SSPIF
SDA
SDA pulled low by other master. Reset BRG and assert SDA.
SCL SEN BCLIF
S
SCL pulled low after BRG time-out Set SEN, enable START sequence if SDA = 1, SCL = 1
'0'
S
SSPIF
SDA = 0, SCL = 1 Set SSPIF Interrupts cleared in software.
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9.4.17.2 Bus Collision During a Repeated START Condition
During a Repeated START condition, a bus collision occurs if: a) b) A low level is sampled on SDA when SCL goes from low level to high level. SCL goes low before SDA is asserted low, indicating that another master is attempting to transmit a data '1'. begins counting. If SDA goes from high to low before the BRG times out, no bus collision occurs because no two masters can assert SDA at exactly the same time. If SCL goes from high to low before the BRG times out and SDA has not already been asserted, a bus collision occurs. In this case, another master is attempting to transmit a data '1' during the Repeated START condition (Figure 9-30). If, at the end of the BRG time-out, both SCL and SDA are still high, the SDA pin is driven low and the BRG is reloaded and begins counting. At the end of the count, regardless of the status of the SCL pin, the SCL pin is driven low and the Repeated START condition is complete.
When the user de-asserts SDA and the pin is allowed to float high, the BRG is loaded with SSPADD<6:0> and counts down to 0. The SCL pin is then de-asserted, and when sampled high, the SDA pin is sampled. If SDA is low, a bus collision has occurred (i.e., another master is attempting to transmit a data '0', Figure 9-29). If SDA is sampled high, the BRG is reloaded and
FIGURE 9-29:
SDA
BUS COLLISION DURING A REPEATED START CONDITION (CASE 1)
SCL Sample SDA when SCL goes high. If SDA = 0, set BCLIF and release SDA and SCL. RSEN BCLIF Cleared in software '0' '0'
S SSPIF
FIGURE 9-30:
BUS COLLISION DURING REPEATED START CONDITION (CASE 2)
TBRG TBRG
SDA SCL BCLIF SCL goes low before SDA, set BCLIF. Release SDA and SCL. Interrupt cleared in software RSEN S SSPIF
'0'
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9.4.17.3 Bus Collision During a STOP Condition
Bus collision occurs during a STOP condition if: a) After the SDA pin has been de-asserted and allowed to float high, SDA is sampled low after the BRG has timed out. After the SCL pin is de-asserted, SCL is sampled low before SDA goes high. The STOP condition begins with SDA asserted low. When SDA is sampled low, the SCL pin is allowed to float. When the pin is sampled high (clock arbitration), the baud rate generator is loaded with SSPADD<6:0> and counts down to 0. After the BRG times out, SDA is sampled. If SDA is sampled low, a bus collision has occurred. This is due to another master attempting to drive a data '0' (Figure 9-31). If the SCL pin is sampled low before SDA is allowed to float high, a bus collision occurs. This is another case of another master attempting to drive a data '0' (Figure 9-32).
b)
FIGURE 9-31:
BUS COLLISION DURING A STOP CONDITION (CASE 1)
TBRG TBRG TBRG
SDA sampled low after TBRG, set BCLIF.
SDA
SDA asserted low
SCL PEN BCLIF P SSPIF
'0' '0'
FIGURE 9-32:
BUS COLLISION DURING A STOP CONDITION (CASE 2)
TBRG TBRG TBRG
SDA
Assert SDA SCL goes low before SDA goes high, set BCLIF.
SCL PEN BCLIF P SSPIF
'0' '0'
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NOTES:
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10.0 ADDRESSABLE UNIVERSAL SYNCHRONOUS ASYNCHRONOUS RECEIVER TRANSMITTER (USART)
The USART can be configured in the following modes: * Asynchronous (full duplex) * Synchronous - Master (half duplex) * Synchronous - Slave (half duplex) Bit SPEN (RCSTA<7>) and bits TRISC<7:6> have to be set in order to configure pins RC6/TX/CK and RC7/RX/DT as the Universal Synchronous Asynchronous Receiver Transmitter. The USART module also has a multi-processor communication capability using 9-bit address detection.
The Universal Synchronous Asynchronous Receiver Transmitter (USART) module is one of the two serial I/O modules. (USART is also known as a Serial Communications Interface or SCI.) The USART can be configured as a full duplex asynchronous system that can communicate with peripheral devices, such as CRT terminals and personal computers, or it can be configured as a half duplex synchronous system that can communicate with peripheral devices, such as A/D or D/A integrated circuits, serial EEPROMs etc.
REGISTER 10-1:
TXSTA: TRANSMIT STATUS AND CONTROL REGISTER (ADDRESS 98h)
R/W-0 CSRC bit 7 R/W-0 TX9 R/W-0 TXEN R/W-0 SYNC U-0 -- R/W-0 BRGH R-1 TRMT R/W-0 TX9D bit 0
bit 7
CSRC: Clock Source Select bit Asynchronous mode: Don't care Synchronous mode: 1 = Master mode (clock generated internally from BRG) 0 = Slave mode (clock from external source) TX9: 9-bit Transmit Enable bit 1 = Selects 9-bit transmission 0 = Selects 8-bit transmission TXEN: Transmit Enable bit 1 = Transmit enabled 0 = Transmit disabled Note: SREN/CREN overrides TXEN in SYNC mode.
bit 6
bit 5
bit 4
SYNC: USART Mode Select bit 1 = Synchronous mode 0 = Asynchronous mode Unimplemented: Read as '0' BRGH: High Baud Rate Select bit Asynchronous mode: 1 = High speed 0 = Low speed Synchronous mode: Unused in this mode TRMT: Transmit Shift Register Status bit 1 = TSR empty 0 = TSR full TX9D: 9th bit of Transmit Data, can be Parity bit Legend: R = Readable bit - n = Value at POR W = Writable bit '1' = Bit is set U = Unimplemented bit, read as `0' '0' = Bit is cleared x = Bit is unknown
bit 3 bit 2
bit 1
bit 0
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REGISTER 10-2: RCSTA: RECEIVE STATUS AND CONTROL REGISTER (ADDRESS 18h)
R/W-0 SPEN bit 7 bit 7 SPEN: Serial Port Enable bit 1 = Serial port enabled (configures RC7/RX/DT and RC6/TX/CK pins as serial port pins) 0 = Serial port disabled RX9: 9-bit Receive Enable bit 1 = Selects 9-bit reception 0 = Selects 8-bit reception SREN: Single Receive Enable bit Asynchronous mode: Don't care Synchronous mode - Master: 1 = Enables single receive 0 = Disables single receive This bit is cleared after reception is complete. Synchronous mode - Slave: Don't care CREN: Continuous Receive Enable bit Asynchronous mode: 1 = Enables continuous receive 0 = Disables continuous receive Synchronous mode: 1 = Enables continuous receive until enable bit CREN is cleared (CREN overrides SREN) 0 = Disables continuous receive ADDEN: Address Detect Enable bit Asynchronous mode 9-bit (RX9 = 1): 1 = Enables address detection, enables interrupt and load of the receive buffer when RSR<8> is set 0 = Disables address detection, all bytes are received, and ninth bit can be used as parity bit FERR: Framing Error bit 1 = Framing error (can be updated by reading RCREG register and receive next valid byte) 0 = No framing error OERR: Overrun Error bit 1 = Overrun error (can be cleared by clearing bit CREN) 0 = No overrun error RX9D: 9th bit of Received Data (can be parity bit, but must be calculated by user firmware) Legend: R = Readable bit - n = Value at POR W = Writable bit '1' = Bit is set U = Unimplemented bit, read as `0' '0' = Bit is cleared x = Bit is unknown R/W-0 RX9 R/W-0 SREN R/W-0 CREN R/W-0 ADDEN R-0 FERR R-0 OERR R-x RX9D bit 0
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
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10.1 USART Baud Rate Generator (BRG)
It may be advantageous to use the high baud rate (BRGH = 1), even for slower baud clocks. This is because the FOSC/(16(X + 1)) equation can reduce the baud rate error in some cases. Writing a new value to the SPBRG register causes the BRG timer to be reset (or cleared). This ensures the BRG does not wait for a timer overflow before outputting the new baud rate.
The BRG supports both the Asynchronous and Synchronous modes of the USART. It is a dedicated 8-bit baud rate generator. The SPBRG register controls the period of a free running 8-bit timer. In Asynchronous mode, bit BRGH (TXSTA<2>) also controls the baud rate. In Synchronous mode, bit BRGH is ignored. Table 10-1 shows the formula for computation of the baud rate for different USART modes which only apply in Master mode (internal clock). Given the desired baud rate and FOSC, the nearest integer value for the SPBRG register can be calculated using the formula in Table 10-1. From this, the error in baud rate can be determined.
10.1.1
SAMPLING
The data on the RC7/RX/DT pin is sampled three times by a majority detect circuit to determine if a high or a low level is present at the RX pin.
TABLE 10-1:
SYNC 0 1
BAUD RATE FORMULA
BRGH = 0 (Low Speed) (Asynchronous) Baud Rate = FOSC/(64(X+1)) (Synchronous) Baud Rate = FOSC/(4(X+1)) BRGH = 1 (High Speed) Baud Rate = FOSC/(16(X+1)) N/A
X = value in SPBRG (0 to 255)
TABLE 10-2:
Address 98h 18h 99h
REGISTERS ASSOCIATED WITH BAUD RATE GENERATOR
Bit 7 CSRC SPEN Bit 6 TX9 RX9 Bit 5 TXEN SREN Bit 4 SYNC CREN Bit 3 -- ADDEN Bit 2 BRGH FERR Bit 1 TRMT OERR Bit 0 TX9D RX9D Value on: POR, BOR
0000 -010 0000 000x 0000 0000
Name TXSTA RCSTA SPBRG
Value on all other RESETS
0000 -010 0000 000x 0000 0000
Baud Rate Generator Register
Legend: x = unknown, - = unimplemented, read as '0'. Shaded cells are not used by the BRG.
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TABLE 10-3:
BAUD RATE (K) 0.3 1.2 2.4 9.6 19.2 28.8 33.6 57.6 HIGH LOW
BAUD RATES FOR ASYNCHRONOUS MODE (BRGH = 0)
FOSC = 20 MHz % ERROR 1.75 0.17 1.73 1.72 8.51 3.34 8.51 FOSC = 4 MHz SPBRG value (decimal) 255 129 31 15 9 8 4 255 0 FOSC = 16 MHz % ERROR 0.17 0.17 0.16 0.16 3.55 6.29 8.51 SPBRG value (decimal) 207 103 25 12 8 6 3 255 0 FOSC = 10 MHz % ERROR 0.17 0.17 1.73 1.72 8.51 6.99 9.58 SPBRG value (decimal) 129 64 15 7 4 4 2 255 0
KBAUD 1.221 2.404 9.766 19.531 31.250 34.722 62.500 1.221 312.500
KBAUD 1.202 2.404 9.615 19.231 27.778 35.714 62.500 0.977 250.000
KBAUD 1.202 2.404 9.766 19.531 31.250 31.250 52.083 0.610 156.250
FOSC = 3.6864 MHz % ERROR 0 0 0 0 0 0 0 SPBRG value (decimal) 191 47 23 5 2 1 0 255 0
BAUD RATE (K) KBAUD 0.3 1.2 2.4 9.6 19.2 28.8 33.6 57.6 HIGH LOW 0.300 1.202 2.404 8.929 20.833 31.250 62.500 0.244 62.500
% ERROR 0 0.17 0.17 6.99 8.51 8.51 8.51 -
SPBRG value (decimal) 207 51 25 6 2 1 0 255 0
KBAUD 0.3 1.2 2.4 9.6 19.2 28.8 57.6 0.225 57.6
TABLE 10-4:
BAUD RATE (K) 0.3 1.2 2.4 9.6 19.2 28.8 33.6 57.6 HIGH LOW BAUD RATE (K) KBAUD 0.3 1.2 2.4 9.6 19.2 28.8 33.6 57.6 HIGH LOW 1.202 2.404 9.615 19.231 27.798 35.714 62.500 0.977 250.000
BAUD RATES FOR ASYNCHRONOUS MODE (BRGH = 1)
FOSC = 20 MHz % ERROR 0.16 0.16 0.94 0.55 3.34 FOSC = 4 MHz % ERROR 0.17 0.17 0.16 0.16 3.55 6.29 8.51 SPBRG value (decimal) 207 103 25 12 8 6 3 255 0 SPBRG value (decimal) 129 64 42 36 20 255 0 FOSC = 16 MHz % ERROR 0.16 0.16 2.13 0.79 2.13 SPBRG value (decimal) 103 51 33 29 16 255 0 FOSC = 10 MHz % ERROR 1.71 0.16 1.72 1.36 2.10 1.36 SPBRG value (decimal) 255 64 31 21 18 10 255 0
KBAUD 9.615 19.231 29.070 33.784 59.524 4.883 1250.000
KBAUD 9.615 19.231 29.412 33.333 58.824 3.906 1000.000
KBAUD 2.441 9.615 19.531 28.409 32.895 56.818 2.441 625.000
FOSC = 3.6864 MHz % ERROR 0 0 0 0 0 2.04 0 SPBRG value (decimal) 191 95 23 11 7 6 3 255 0
KBAUD 1.2 2.4 9.6 19.2 28.8 32.9 57.6 0.9 230.4
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10.2 USART Asynchronous Mode
In this mode, the USART uses standard non-return-tozero (NRZ) format (one START bit, eight or nine data bits, and one STOP bit). The most common data format is 8-bits. An on-chip, dedicated, 8-bit baud rate generator can be used to derive standard baud rate frequencies from the oscillator. The USART transmits and receives the LSb first. The transmitter and receiver are functionally independent, but use the same data format and baud rate. The baud rate generator produces a clock, either x16 or x64 of the bit shift rate, depending on bit BRGH (TXSTA<2>). Parity is not supported by the hardware, but can be implemented in software (and stored as the ninth data bit). Asynchronous mode is stopped during SLEEP. Asynchronous mode is selected by clearing bit SYNC (TXSTA<4>). The USART Asynchronous module consists of the following important elements: * * * * Baud Rate Generator Sampling Circuit Asynchronous Transmitter Asynchronous Receiver enabled/disabled by setting/clearing enable bit, TXIE ( PIE1<4>). Flag bit TXIF will be set, regardless of the state of enable bit TXIE and cannot be cleared in software. It will reset only when new data is loaded into the TXREG register. While flag bit TXIF indicates the status of the TXREG register, another bit, TRMT (TXSTA<1>), shows the status of the TSR register. Status bit TRMT is a read only bit, which is set when the TSR register is empty. No interrupt logic is tied to this bit, so the user has to poll this bit in order to determine if the TSR register is empty. Note 1: The TSR register is not mapped in data memory, so it is not available to the user. 2: Flag bit TXIF is set when enable bit TXEN is set. TXIF is cleared by loading TXREG. Transmission is enabled by setting enable bit TXEN (TXSTA<5>). The actual transmission will not occur until the TXREG register has been loaded with data and the baud rate generator (BRG) has produced a shift clock (Figure 10-2). The transmission can also be started by first loading the TXREG register and then setting enable bit TXEN. Normally, when transmission is first started, the TSR register is empty. At that point, transfer to the TXREG register will result in an immediate transfer to TSR, resulting in an empty TXREG. A back-to-back transfer is thus possible (Figure 10-3). Clearing enable bit TXEN during a transmission will cause the transmission to be aborted and will reset the transmitter. As a result, the RC6/TX/CK pin will revert to hi-impedance. In order to select 9-bit transmission, transmit bit TX9 (TXSTA<6>) should be set and the ninth bit should be written to TX9D (TXSTA<0>). The ninth bit must be written before writing the 8-bit data to the TXREG register. This is because a data write to the TXREG register can result in an immediate transfer of the data to the TSR register (if the TSR is empty). In such a case, an incorrect ninth data bit may be loaded in the TSR register.
10.2.1
USART ASYNCHRONOUS TRANSMITTER
The USART transmitter block diagram is shown in Figure 10-1. The heart of the transmitter is the transmit (serial) shift register (TSR). The shift register obtains its data from the read/write transmit buffer, TXREG. The TXREG register is loaded with data in software. The TSR register is not loaded until the STOP bit has been transmitted from the previous load. As soon as the STOP bit is transmitted, the TSR is loaded with new data from the TXREG register (if available). Once the TXREG register transfers the data to the TSR register (occurs in one TCY), the TXREG register is empty and flag bit TXIF (PIR1<4>) is set. This interrupt can be
FIGURE 10-1:
USART TRANSMIT BLOCK DIAGRAM
Data Bus TXIF TXREG Register 8 MSb (8) Interrupt TXEN Baud Rate CLK TRMT SPBRG Baud Rate Generator TX9 TX9D SPEN
***
TXIE
LSb 0
Pin Buffer and Control RC6/TX/CK pin
TSR Register
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When setting up an Asynchronous Transmission, follow these steps: 1. Initialize the SPBRG register for the appropriate baud rate. If a high speed baud rate is desired, set bit BRGH (Section 10.1). Enable the asynchronous serial port by clearing bit SYNC and setting bit SPEN. If interrupts are desired, then set enable bit TXIE. If 9-bit transmission is desired, then set transmit bit TX9. 5. 6. 7. 8. Enable the transmission by setting bit TXEN, which will also set bit TXIF. If 9-bit transmission is selected, the ninth bit should be loaded in bit TX9D. Load data to the TXREG register (starts transmission). If using interrupts, ensure that GIE and PEIE (bits 7 and 6) of the INTCON register are set.
2. 3. 4.
FIGURE 10-2:
Write to TXREG BRG Output (Shift Clock) RC6/TX/CK (pin) TXIF bit (Transmit Buffer Reg. Empty Flag)
ASYNCHRONOUS MASTER TRANSMISSION
Word 1
START Bit
Bit 0
Bit 1 Word 1
Bit 7/8
STOP Bit
TRMT bit (Transmit Shift Reg. Empty Flag)
Word 1 Transmit Shift Reg
FIGURE 10-3:
Write to TXREG BRG Output (Shift Clock) RC6/TX/CK (pin) TXIF bit (Interrupt Reg. Flag) TRMT bit (Transmit Shift Reg. Empty Flag)
ASYNCHRONOUS MASTER TRANSMISSION (BACK TO BACK)
Word 1 Word 2
START Bit
Bit 0
Bit 1 Word 1
Bit 7/8
STOP Bit START Bit Word 2
Bit 0
Word 1 Transmit Shift Reg.
Word 2 Transmit Shift Reg.
Note:
This timing diagram shows two consecutive transmissions.
TABLE 10-5:
Address
REGISTERS ASSOCIATED WITH ASYNCHRONOUS TRANSMISSION
Bit 7 GIE PSPIF(1) SPEN PSPIE(1) CSRC Bit 6 PEIE ADIF RX9 ADIE TX9 Bit 5 TMR0IE RCIF SREN RCIE TXEN Bit 4 INTE TXIF CREN TXIE SYNC Bit 3 RBIE SSPIF -- Bit 2 TMR0IF CCP1IF FERR Bit 1 INTF TMR2IF OERR TMR2IE TRMT Bit 0 R0IF TMR1IF RX9D TMR1IE TX9D Value on: POR, BOR
0000 000x 0000 0000 0000 -00x 0000 0000 0000 0000 0000 -010 0000 0000
Name
Value on all other RESETS
0000 000u 0000 0000 0000 -00x 0000 0000 0000 0000 0000 -010 0000 0000
0Bh, 8Bh, INTCON 10Bh,18Bh 0Ch 18h 19h 8Ch 98h 99h PIR1 RCSTA TXREG PIE1 TXSTA
USART Transmit Register SSPIE CCP1IE -- BRGH
SPBRG Baud Rate Generator Register
Legend: x = unknown, - = unimplemented locations read as '0'. Shaded cells are not used for asynchronous transmission. Note 1: Bits PSPIE and PSPIF are reserved on 28-pin devices; always maintain these bits clear.
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10.2.2 USART ASYNCHRONOUS RECEIVER
is possible for two bytes of data to be received and transferred to the RCREG FIFO and a third byte to begin shifting to the RSR register. On the detection of the STOP bit of the third byte, if the RCREG register is still full, the overrun error bit OERR (RCSTA<1>) will be set. The word in the RSR will be lost. The RCREG register can be read twice to retrieve the two bytes in the FIFO. Overrun bit OERR has to be cleared in software. This is done by resetting the receive logic (CREN is cleared and then set). If bit OERR is set, transfers from the RSR register to the RCREG register are inhibited, and no further data will be received. It is therefore, essential to clear error bit OERR if it is set. Framing error bit FERR (RCSTA<2>) is set if a STOP bit is detected as clear. Bit FERR and the 9th receive bit are buffered the same way as the receive data. Reading the RCREG will load bits RX9D and FERR with new values, therefore, it is essential for the user to read the RCSTA register before reading the RCREG register in order not to lose the old FERR and RX9D information.
The receiver block diagram is shown in Figure 10-4. The data is received on the RC7/RX/DT pin and drives the data recovery block. The data recovery block is actually a high speed shifter, operating at x16 times the baud rate; whereas, the main receive serial shifter operates at the bit rate or at FOSC. Once Asynchronous mode is selected, reception is enabled by setting bit CREN (RCSTA<4>). The heart of the receiver is the receive (serial) shift register (RSR). After sampling the STOP bit, the received data in the RSR is transferred to the RCREG register (if it is empty). If the transfer is complete, flag bit RCIF (PIR1<5>) is set. The actual interrupt can be enabled/ disabled by setting/clearing enable bit RCIE (PIE1<5>). Flag bit RCIF is a read only bit, which is cleared by the hardware. It is cleared when the RCREG register has been read and is empty. The RCREG is a double buffered register (i.e., it is a two deep FIFO). It
FIGURE 10-4:
USART RECEIVE BLOCK DIAGRAM
x64 Baud Rate CLK CREN OERR FERR
FOSC
SPBRG Baud Rate Generator
/64 or /16
MSb STOP (8) 7
RSR Register
***
LSb 0 START
1
RC7/RX/DT Pin Buffer and Control Data Recovery RX9
SPEN
RX9D
RCREG Register
FIFO
8 Interrupt RCIF RCIE Data Bus
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FIGURE 10-5:
RX (pin) Rcv Shift Reg Rcv Buffer Reg Read Rcv Buffer Reg RCREG RCIF (Interrupt Flag) OERR bit CREN Note: This timing diagram shows three words appearing on the RX input. The RCREG (receive buffer) is read after the third word, causing the OERR (overrun) bit to be set.
ASYNCHRONOUS RECEPTION
START bit bit0 bit1 bit7/8 STOP bit START bit bit0 bit7/8 STOP bit START bit bit7/8 STOP bit
Word 1 RCREG
Word 2 RCREG
When setting up an Asynchronous Reception, follow these steps: 1. Initialize the SPBRG register for the appropriate baud rate. If a high speed baud rate is desired, set bit BRGH (Section 10.1). Enable the asynchronous serial port by clearing bit SYNC and setting bit SPEN. If interrupts are desired, then set enable bit RCIE. If 9-bit reception is desired, then set bit RX9. Enable the reception by setting bit CREN.
2. 3. 4. 5.
Flag bit RCIF will be set when reception is complete and an interrupt will be generated if enable bit RCIE is set. 7. Read the RCSTA register to get the ninth bit (if enabled) and determine if any error occurred during reception. 8. Read the 8-bit received data by reading the RCREG register. 9. If any error occurred, clear the error by clearing enable bit CREN. 10. If using interrupts, ensure that GIE and PEIE (bits 7 and 6) of the INTCON register are set.
6.
TABLE 10-6:
Address
REGISTERS ASSOCIATED WITH ASYNCHRONOUS RECEPTION
Bit 7 GIE PSPIF(1) SPEN
(1)
Name
Bit 6 PEIE ADIF RX9
Bit 5 TMR0IE RCIF SREN
Bit 4 INTE TXIF CREN
Bit 3 RBIE SSPIF --
Bit 2 TMR0IF
Bit 1 INTF
Bit 0 R0IF
Value on: POR, BOR
0000 000x 0000 0000 0000 -00x 0000 0000
Value on all other RESETS
0000 000u 0000 0000 0000 -00x 0000 0000 0000 0000 0000 -010 0000 0000
0Bh, 8Bh, INTCON 10Bh,18Bh 0Ch 18h 1Ah 8Ch 98h 99h PIR1 RCSTA
CCP1IF TMR2IF TMR1IF FERR OERR RX9D
RCREG USART Receive Register PIE1 TXSTA SPBRG PSPIE ADIE TX9 RCIE TXEN TXIE SYNC SSPIE CCP1IE TMR2IE TMR1IE -- BRGH TRMT TX9D
0000 0000 0000 -010 0000 0000
CSRC
Baud Rate Generator Register
Legend: x = unknown, - = unimplemented locations read as '0'. Shaded cells are not used for asynchronous reception. Note 1: Bits PSPIE and PSPIF are reserved on 28-pin devices; always maintain these bits clear.
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10.2.3 SETTING UP 9-BIT MODE WITH ADDRESS DETECT
* Flag bit RCIF will be set when reception is complete, and an interrupt will be generated if enable bit RCIE was set. * Read the RCSTA register to get the ninth bit and determine if any error occurred during reception. * Read the 8-bit received data by reading the RCREG register, to determine if the device is being addressed. * If any error occurred, clear the error by clearing enable bit CREN. * If the device has been addressed, clear the ADDEN bit to allow data bytes and address bytes to be read into the receive buffer, and interrupt the CPU.
When setting up an Asynchronous Reception with Address Detect Enabled: * Initialize the SPBRG register for the appropriate baud rate. If a high speed baud rate is desired, set bit BRGH. * Enable the asynchronous serial port by clearing bit SYNC and setting bit SPEN. * If interrupts are desired, then set enable bit RCIE. * Set bit RX9 to enable 9-bit reception. * Set ADDEN to enable address detect. * Enable the reception by setting enable bit CREN.
FIGURE 10-6:
USART RECEIVE BLOCK DIAGRAM
x64 Baud Rate CLK CREN OERR FERR
FOSC
SPBRG
/ 64
Baud Rate Generator RC7/RX/DT Pin Buffer and Control Data Recovery RX9 or / 16
MSb STOP (8) 7
RSR Register
***
LSb 0 START
1
8 SPEN
RX9 ADDEN RX9 ADDEN RSR<8>
Enable Load of Receive Buffer 8
RX9D
RCREG Register FIFO
8 Interrupt RCIF RCIE Data Bus
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FIGURE 10-7:
RC7/RX/DT (pin)
ASYNCHRONOUS RECEPTION WITH ADDRESS DETECT
START bit bit0 bit1 bit8 STOP bit START bit0 bit bit8 STOP bit
Load RSR Bit8 = 0, Data Byte Read Bit8 = 1, Address Byte Word 1 RCREG
RCIF
Note:
This timing diagram shows a data byte followed by an address byte. The data byte is not read into the RCREG (receive buffer) because ADDEN = 1.
FIGURE 10-8:
RC7/RX/DT (pin)
ASYNCHRONOUS RECEPTION WITH ADDRESS BYTE FIRST
START bit bit0 bit1 bit8 STOP bit START bit bit0 bit8 STOP bit
Load RSR Bit8 = 1, Address Byte Read Bit8 = 0, Data Byte Word 1 RCREG
RCIF
Note:
This timing diagram shows a data byte followed by an address byte. The data byte is not read into the RCREG (receive buffer) because ADDEN was not updated and still = 0.
TABLE 10-7:
Address
REGISTERS ASSOCIATED WITH ASYNCHRONOUS RECEPTION
Bit 7 GIE PSPIF(1) SPEN PSPIE(1) CSRC Bit 6 PEIE ADIF RX9 ADIE TX9 Bit 5 TMR0IE RCIF SREN RCIE TXEN Bit 4 INTE TXIF Bit 3 RBIE SSPIF Bit 2 TMR0IF Bit 1 INTF Bit 0 R0IF Value on: POR, BOR
0000 000x
Name
Value on all other RESETS
0000 000u 0000 0000 0000 000x 0000 0000 0000 0000 0000 -010 0000 0000
0Bh, 8Bh, INTCON 10Bh,18Bh 0Ch 18h 1Ah 8Ch 98h 99h PIR1 RCSTA RCREG PIE1 TXSTA SPBRG
CCP1IF TMR2IF TMR1IF 0000 0000 FERR OERR RX9D
0000 000x 0000 0000
CREN ADDEN TXIE SYNC SSPIE --
USART Receive Register BRGH TRMT TX9D
CCP1IE TMR2IE TMR1IE 0000 0000
0000 -010 0000 0000
Baud Rate Generator Register
Legend: x = unknown, - = unimplemented locations read as '0'. Shaded cells are not used for asynchronous reception. Note 1: Bits PSPIE and PSPIF are reserved on 28-pin devices; always maintain these bits clear.
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10.3 USART Synchronous Master Mode
Clearing enable bit TXEN during a transmission will cause the transmission to be aborted and will reset the transmitter. The DT and CK pins will revert to hiimpedance. If either bit CREN or bit SREN is set during a transmission, the transmission is aborted and the DT pin reverts to a hi-impedance state (for a reception). The CK pin will remain an output if bit CSRC is set (internal clock). The transmitter logic, however, is not reset, although it is disconnected from the pins. In order to reset the transmitter, the user has to clear bit TXEN. If bit SREN is set (to interrupt an on-going transmission and receive a single word), then after the single word is received, bit SREN will be cleared and the serial port will revert back to transmitting, since bit TXEN is still set. The DT line will immediately switch from hiimpedance Receive mode to transmit and start driving. To avoid this, bit TXEN should be cleared. In order to select 9-bit transmission, the TX9 (TXSTA<6>) bit should be set and the ninth bit should be written to bit TX9D (TXSTA<0>). The ninth bit must be written before writing the 8-bit data to the TXREG register. This is because a data write to the TXREG can result in an immediate transfer of the data to the TSR register (if the TSR is empty). If the TSR was empty and the TXREG was written before writing the "new" TX9D, the "present" value of bit TX9D is loaded. Steps to follow when setting up a Synchronous Master Transmission: 1. 2. 3. 4. 5. 6. 7. 8. Initialize the SPBRG register for the appropriate baud rate (Section 10.1). Enable the synchronous master serial port by setting bits SYNC, SPEN and CSRC. If interrupts are desired, set enable bit TXIE. If 9-bit transmission is desired, set bit TX9. Enable the transmission by setting bit TXEN. If 9-bit transmission is selected, the ninth bit should be loaded in bit TX9D. Start transmission by loading data to the TXREG register. If using interrupts, ensure that GIE and PEIE (bits 7 and 6) of the INTCON register are set.
In Synchronous Master mode, the data is transmitted in a half-duplex manner (i.e., transmission and reception do not occur at the same time). When transmitting data, the reception is inhibited and vice versa. Synchronous mode is entered by setting bit SYNC (TXSTA<4>). In addition, enable bit SPEN (RCSTA<7>) is set in order to configure the RC6/TX/CK and RC7/RX/DT I/O pins to CK (clock) and DT (data) lines, respectively. The Master mode indicates that the processor transmits the master clock on the CK line. The Master mode is entered by setting bit CSRC (TXSTA<7>).
10.3.1
USART SYNCHRONOUS MASTER TRANSMISSION
The USART transmitter block diagram is shown in Figure 10-6. The heart of the transmitter is the transmit (serial) shift register (TSR). The shift register obtains its data from the read/write transmit buffer register, TXREG. The TXREG register is loaded with data in software. The TSR register is not loaded until the last bit has been transmitted from the previous load. As soon as the last bit is transmitted, the TSR is loaded with new data from the TXREG (if available). Once the TXREG register transfers the data to the TSR register (occurs in one TCYCLE), the TXREG is empty and interrupt bit TXIF (PIR1<4>) is set. The interrupt can be enabled/disabled by setting/clearing enable bit TXIE (PIE1<4>). Flag bit TXIF will be set, regardless of the state of enable bit TXIE and cannot be cleared in software. It will reset only when new data is loaded into the TXREG register. While flag bit TXIF indicates the status of the TXREG register, another bit TRMT (TXSTA<1>) shows the status of the TSR register. TRMT is a read only bit which is set when the TSR is empty. No interrupt logic is tied to this bit, so the user has to poll this bit in order to determine if the TSR register is empty. The TSR is not mapped in data memory, so it is not available to the user. Transmission is enabled by setting enable bit TXEN (TXSTA<5>). The actual transmission will not occur until the TXREG register has been loaded with data. The first data bit will be shifted out on the next available rising edge of the clock on the CK line. Data out is stable around the falling edge of the synchronous clock (Figure 10-9). The transmission can also be started by first loading the TXREG register and then setting bit TXEN (Figure 10-10). This is advantageous when slow baud rates are selected, since the BRG is kept in RESET when bits TXEN, CREN and SREN are clear. Setting enable bit TXEN will start the BRG, creating a shift clock immediately. Normally, when transmission is first started, the TSR register is empty, so a transfer to the TXREG register will result in an immediate transfer to TSR, resulting in an empty TXREG. Back-to-back transfers are possible.
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TABLE 10-8:
Address
REGISTERS ASSOCIATED WITH SYNCHRONOUS MASTER TRANSMISSION
Bit 7 GIE PSPIF(1) SPEN PSPIE(1) CSRC Bit 6 PEIE ADIF RX9 Bit 5 TMR0IE RCIF SREN Bit 4 INTE TXIF CREN Bit 3 RBIE SSPIF -- Bit 2 TMR0IF CCP1IF FERR Bit 1 INTF TMR2IF OERR Bit 0 R0IF TMR1IF RX9D Value on: POR, BOR
0000 000x 0000 0000 0000 -00x 0000 0000
Name
Value on all other RESETS
0000 000u 0000 0000 0000 -00x 0000 0000 0000 0000 0000 -010 0000 0000
0Bh, 8Bh, INTCON 10Bh,18Bh 0Ch 18h 19h 8Ch 98h 99h PIR1 RCSTA TXREG PIE1 TXSTA SPBRG
USART Transmit Register ADIE TX9 RCIE TXEN TXIE SYNC SSPIE --
CCP1IE TMR2IE TMR1IE 0000 0000 BRGH TRMT TX9D
0000 -010 0000 0000
Baud Rate Generator Register
Legend: x = unknown, - = unimplemented, read as '0'. Shaded cells are not used for synchronous master transmission. Note 1: Bits PSPIE and PSPIF are reserved on 28-pin devices; always maintain these bits clear.
FIGURE 10-9:
SYNCHRONOUS TRANSMISSION
Q3 Q4 Q1 Q2 Q3Q4 Q1Q2 Q3 Q4 Q1 Q2Q3 Q4Q1 Q2 Q3 Q4 Q1Q2 Q3 Q4 Q1 Q2 Q3 Q4
Q1Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1Q2Q3 Q4Q1Q2 Q3 Q4Q1 Q2 Q3 Q4
RC7/RX/DT pin RC6/TX/CK pin Write to TXREG reg Write Word 1 TXIF bit (Interrupt Flag) TRMT bit '1'
bit 0
bit 1 Word 1
bit 2
bit 7
bit 0
bit 1 Word 2
bit 7
Write Word 2
TXEN bit
'1'
Note: Sync Master mode; SPBRG = '0'. Continuous transmission of two 8-bit words.
FIGURE 10-10:
SYNCHRONOUS TRANSMISSION (THROUGH TXEN)
bit0 bit1 bit2 bit6 bit7
RC7/RX/DT pin RC6/TX/CK pin
Write to TXREG Reg
TXIF bit
TRMT bit
TXEN bit
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10.3.2 USART SYNCHRONOUS MASTER RECEPTION
receive bit is buffered the same way as the receive data. Reading the RCREG register will load bit RX9D with a new value, therefore, it is essential for the user to read the RCSTA register before reading RCREG, in order not to lose the old RX9D information. When setting up a Synchronous Master Reception: Initialize the SPBRG register for the appropriate baud rate (Section 10.1). 2. Enable the synchronous master serial port by setting bits SYNC, SPEN and CSRC. 3. Ensure bits CREN and SREN are clear. 4. If interrupts are desired, then set enable bit RCIE. 5. If 9-bit reception is desired, then set bit RX9. 6. If a single reception is required, set bit SREN. For continuous reception, set bit CREN. 7. Interrupt flag bit RCIF will be set when reception is complete and an interrupt will be generated if enable bit RCIE was set. 8. Read the RCSTA register to get the ninth bit (if enabled) and determine if any error occurred during reception. 9. Read the 8-bit received data by reading the RCREG register. 10. If any error occurred, clear the error by clearing bit CREN. 11. If using interrupts, ensure that GIE and PEIE (bits 7 and 6) of the INTCON register are set. 1.
Once Synchronous mode is selected, reception is enabled by setting either enable bit SREN (RCSTA<5>), or enable bit CREN (RCSTA<4>). Data is sampled on the RC7/RX/DT pin on the falling edge of the clock. If enable bit SREN is set, then only a single word is received. If enable bit CREN is set, the reception is continuous until CREN is cleared. If both bits are set, CREN takes precedence. After clocking the last bit, the received data in the Receive Shift Register (RSR) is transferred to the RCREG register (if it is empty). When the transfer is complete, interrupt flag bit RCIF (PIR1<5>) is set. The actual interrupt can be enabled/ disabled by setting/clearing enable bit RCIE (PIE1<5>). Flag bit RCIF is a read only bit, which is reset by the hardware. In this case, it is reset when the RCREG register has been read and is empty. The RCREG is a double buffered register (i.e., it is a two deep FIFO). It is possible for two bytes of data to be received and transferred to the RCREG FIFO and a third byte to begin shifting into the RSR register. On the clocking of the last bit of the third byte, if the RCREG register is still full, then overrun error bit OERR (RCSTA<1>) is set. The word in the RSR will be lost. The RCREG register can be read twice to retrieve the two bytes in the FIFO. Bit OERR has to be cleared in software (by clearing bit CREN). If bit OERR is set, transfers from the RSR to the RCREG are inhibited, so it is essential to clear bit OERR if it is set. The ninth
TABLE 10-9:
Address
REGISTERS ASSOCIATED WITH SYNCHRONOUS MASTER RECEPTION
Bit 7 GIE PSPIF(1) SPEN PSPIE(1) CSRC Bit 6 PEIE ADIF RX9 ADIE TX9 Bit 5 TMR0IE RCIF SREN RCIE TXEN Bit 4 INTE TXIF CREN TXIE SYNC Bit 3 RBIE SSPIF -- SSPIE -- Bit 2 TMR0IF CCP1IF FERR Bit 1 INTF TMR2IF OERR Bit 0 R0IF TMR1IF RX9D Value on: POR, BOR
0000 000x 0000 0000 0000 -00x 0000 0000
Name
Value on all other RESETS
0000 000u 0000 0000 0000 -00x 0000 0000 0000 0000 0000 -010 0000 0000
0Bh, 8Bh, INTCON 10Bh,18Bh 0Ch 18h 1Ah 8Ch 98h 99h PIR1 RCSTA RCREG PIE1 TXSTA SPBRG
USART Receive Register BRGH TRMT TX9D
CCP1IE TMR2IE TMR1IE 0000 0000
0000 -010 0000 0000
Baud Rate Generator Register
Legend: x = unknown, - = unimplemented, read as '0'. Shaded cells are not used for synchronous master reception. Note 1: Bits PSPIE and PSPIF are reserved on 28-pin devices; always maintain these bits clear.
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FIGURE 10-11: SYNCHRONOUS RECEPTION (MASTER MODE, SREN)
Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4
RC7/RX/DT pin RC6/TX/CK pin Write to bit SREN SREN bit CREN bit RCIF bit (Interrupt) Read RXREG '0'
bit0
bit1
bit2
bit3
bit4
bit5
bit6
bit7
'0'
Note: Timing diagram demonstrates SYNC Master mode with bit SREN = '1' and bit BRG = '0'.
10.4
USART Synchronous Slave Mode
Synchronous Slave mode differs from the Master mode in the fact that the shift clock is supplied externally at the RC6/TX/CK pin (instead of being supplied internally in Master mode). This allows the device to transfer or receive data while in SLEEP mode. Slave mode is entered by clearing bit CSRC (TXSTA<7>).
When setting up a Synchronous Slave Transmission, follow these steps: 1. Enable the synchronous slave serial port by setting bits SYNC and SPEN and clearing bit CSRC. Clear bits CREN and SREN. If interrupts are desired, then set enable bit TXIE. If 9-bit transmission is desired, then set bit TX9. Enable the transmission by setting enable bit TXEN. If 9-bit transmission is selected, the ninth bit should be loaded in bit TX9D. Start transmission by loading data to the TXREG register. If using interrupts, ensure that GIE and PEIE (bits 7 and 6) of the INTCON register are set.
2. 3. 4. 5. 6. 7. 8.
10.4.1
USART SYNCHRONOUS SLAVE TRANSMIT
The operation of the Synchronous Master and Slave modes is identical, except in the case of the SLEEP mode. If two words are written to the TXREG and then the SLEEP instruction is executed, the following will occur: a) b) c) d) The first word will immediately transfer to the TSR register and transmit. The second word will remain in TXREG register. Flag bit TXIF will not be set. When the first word has been shifted out of TSR, the TXREG register will transfer the second word to the TSR and flag bit TXIF will now be set. If enable bit TXIE is set, the interrupt will wake the chip from SLEEP and if the global interrupt is enabled, the program will branch to the interrupt vector (0004h).
e)
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TABLE 10-10: REGISTERS ASSOCIATED WITH SYNCHRONOUS SLAVE TRANSMISSION
Address Name Bit 7 GIE PSPIF(1) SPEN PSPIE(1) CSRC Bit 6 PEIE ADIF RX9 ADIE TX9 Bit 5 TMR0IE RCIF SREN RCIE TXEN Bit 4 INTE TXIF CREN TXIE SYNC Bit 3 RBIE SSPIF ADDEN SSPIE -- Bit 2 TMR0IF Bit 1 INTF Bit 0 R0IF Value on: POR, BOR
0000 000x
Value on all other RESETS
0000 000u
0Bh, 8Bh, INTCON 10Bh,18Bh 0Ch 18h 19h 8Ch 98h 99h PIR1 RCSTA TXREG PIE1 TXSTA SPBRG
CCP1IF TMR2IF TMR1IF 0000 0000 0000 0000 FERR OERR RX9D
0000 000x 0000 000x 0000 0000 0000 0000
USART Transmit Register BRGH TRMT TX9D
CCP1IE TMR2IE TMR1IE 0000 0000 0000 0000
0000 -010 0000 -010 0000 0000 0000 0000
Baud Rate Generator Register
Legend: x = unknown, - = unimplemented, read as '0'. Shaded cells are not used for synchronous slave transmission. Note 1: Bits PSPIE and PSPIF are reserved on 28-pin devices; always maintain these bits clear.
10.4.2
USART SYNCHRONOUS SLAVE RECEPTION
When setting up a Synchronous Slave Reception, follow these steps: 1. Enable the synchronous master serial port by setting bits SYNC and SPEN and clearing bit CSRC. If interrupts are desired, set enable bit RCIE. If 9-bit reception is desired, set bit RX9. To enable reception, set enable bit CREN. Flag bit RCIF will be set when reception is complete and an interrupt will be generated, if enable bit RCIE was set. Read the RCSTA register to get the ninth bit (if enabled) and determine if any error occurred during reception. Read the 8-bit received data by reading the RCREG register. If any error occurred, clear the error by clearing bit CREN. If using interrupts, ensure that GIE and PEIE (bits 7 and 6) of the INTCON register are set.
The operation of the Synchronous Master and Slave modes is identical, except in the case of the SLEEP mode. Bit SREN is a "don't care" in Slave mode. If receive is enabled by setting bit CREN prior to the SLEEP instruction, then a word may be received during SLEEP. On completely receiving the word, the RSR register will transfer the data to the RCREG register and if enable bit RCIE bit is set, the interrupt generated will wake the chip from SLEEP. If the global interrupt is enabled, the program will branch to the interrupt vector (0004h).
2. 3. 4. 5.
6.
7. 8. 9.
TABLE 10-11: REGISTERS ASSOCIATED WITH SYNCHRONOUS SLAVE RECEPTION
Address Name Bit 7 GIE PSPIF(1) SPEN PSPIE(1) CSRC Bit 6 PEIE ADIF RX9 ADIE TX9 Bit 5 TMR0IE RCIF SREN RCIE TXEN Bit 4 INTE TXIF CREN TXIE SYNC Bit 3 RBIE SSPIF ADDEN SSPIE -- Bit 2 TMR0IF CCP1IF FERR Bit 1 INTF TMR2IF OERR Bit 0 R0IF Value on: POR, BOR
0000 000x
Value on all other RESETS
0000 000u
0Bh, 8Bh, INTCON 10Bh,18Bh 0Ch 18h 1Ah 8Ch 98h 99h PIR1 RCSTA RCREG PIE1 TXSTA SPBRG
TMR1IF 0000 0000 0000 0000 RX9D
0000 000x 0000 000x 0000 0000 0000 0000
USART Receive Register BRGH TRMT TX9D
CCP1IE TMR2IE TMR1IE 0000 0000 0000 0000
0000 -010 0000 -010 0000 0000 0000 0000
Baud Rate Generator Register
Legend: x = unknown, - = unimplemented, read as '0'. Shaded cells are not used for synchronous slave reception. Note 1: Bits PSPIE and PSPIF are reserved on 28-pin devices, always maintain these bits clear.
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NOTES:
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11.0 ANALOG-TO-DIGITAL CONVERTER (A/D) MODULE
The A/D module has four registers. These registers are: * * * * A/D Result High Register (ADRESH) A/D Result Low Register (ADRESL) A/D Control Register0 (ADCON0) A/D Control Register1 (ADCON1) The Analog-to-Digital (A/D) Converter module has five inputs for the 28-pin devices and eight for the 40/44-pin devices. The conversion of an analog input signal results in a corresponding 10-bit digital number. The A/D module has high and low voltage reference input, that is software selectable to some combination of VDD, VSS, RA2, or RA3. The A/D converter has a unique feature of being able to operate while the device is in SLEEP mode. To operate in SLEEP, the A/D clock must be derived from the A/D's internal RC oscillator.
The ADCON0 register, shown in Register 11-1, controls the operation of the A/D module. The ADCON1 register, shown in Register 11-2, configures the functions of the port pins. The port pins can be configured as analog inputs (RA3 can also be the voltage reference), or as digital I/O. Additional information on using the A/D module can be found in the PICmicroTM Mid-Range MCU Family Reference Manual (DS33023).
REGISTER 11-1:
ADCON0 REGISTER (ADDRESS 1Fh)
R/W-0 ADCS1 bit 7 R/W-0 ADCS0 R/W-0 CHS2 R/W-0 CHS1 R/W-0 CHS0 R/W-0 GO/DONE
U-0 --
R/W-0 ADON bit 0
bit 7-6
ADCS1:ADCS0: A/D Conversion Clock Select bits (ADCON0 bits in bold) ADCON1
0 0 0 0 1 1 1 1
ADCON0
00 01 10 11 00 01 10 11
Clock Conversion FOSC/2 FOSC/8 FOSC/32 FRC (clock derived from the internal A/D RC oscillator) FOSC/4 FOSC/16 FOSC/64 FRC (clock derived from the internal A/D RC oscillator)
bit 5-3
CHS2:CHS0: Analog Channel Select bits 000 = Channel 0 (AN0) 001 = Channel 1 (AN1) 010 = Channel 2 (AN2) 011 = Channel 3 (AN3) 100 = Channel 4 (AN4) 101 = Channel 5 (AN5) 110 = Channel 6 (AN6) 111 = Channel 7 (AN7) Note: The PIC16F873A/876A devices only implement A/D channels 0 through 4; the unimplemented selections are reserved. Do not select any unimplemented channels with these devices.
bit 2
GO/DONE: A/D Conversion Status bit When ADON = 1: 1 = A/D conversion in progress (setting this bit starts the A/D conversion which is automatically cleared by hardware when the A/D conversion is complete) 0 = A/D conversion not in progress Unimplemented: Read as '0' ADON: A/D On bit 1 = A/D converter module is powered up 0 = A/D converter module is shut-off and consumes no operating current Legend: R = Readable bit - n = Value at POR reset W = Writable bit '1' = Bit is set U = Unimplemented bit, read as `0' '0' = Bit is cleared x = Bit is unknown
bit 1 bit 0
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REGISTER 11-2: ADCON1 REGISTER (ADDRESS 9Fh)
R/W-0 ADFM bit 7 bit 7 ADFM: A/D Result Format Select.bit 1 = Right justified. Six (6) Most Significant bits of ADRESH are read as '0'. 0 = Left justified. Six (6) Least Significant bits of ADRESL are read as '0'. ADCS2: A/D Conversion Clock Select bit (ADCON1 bits in shaded area and in bold) ADCON1 ADCON0 0 0 0 0 1 1 1 1 bit 5-4 bit 3-0 00 01 10 11 00 01 10 11 Clock Conversion FOSC/2 FOSC/8 FOSC/32 FRC (clock derived from the internal A/D RC oscillator) FOSC/4 FOSC/16 FOSC/64 FRC (clock derived from the internal A/D RC oscillator) R/W-0 ADCS2 U-0 -- U-0 -- R/W-0 PCFG3 R/W-0 PCFG2 R/W-0 PCFG1 R/W-0 PCFG0 bit 0
bit 6
Unimplemented: Read as '0' PCFG3:PCFG0: A/D Port Configuration Control bits PCFG <3:0> 0000 0001 0010 0011 0100 0101 011x 1000 1001 1010 1011 1100 1101 1110 1111 AN7 A A D D D D D A D D D D D D D AN6 A A D D D D D A D D D D D D D AN5 A A D D D D D A A A A D D D D AN4 A A A A D D D A A A A A D D D AN3 A VREF+ A VREF+ A VREF+ D VREF+ A VREF+ VREF+ VREF+ VREF+ D VREF+ AN2 A A A A D D D VREFA A VREFVREFVREFD VREFAN1 A A A A A A D A A A A A A D D AN0 A A A A A A D A A A A A A A A VREF+ VDD AN3 VDD AN3 VDD AN3 -- AN3 VDD AN3 AN3 AN3 AN3 VDD AN3 VREFVSS VSS VSS VSS VSS VSS -- AN2 VSS VSS AN2 AN2 AN2 VSS AN2 C/R 8/0 7/1 5/0 4/1 3/0 2/1 0/0 6/2 6/0 5/1 4/2 3/2 2/2 1/0 1/2
A = Analog input D = Digital I/O C / R = # of analog input channels / # of A/D voltage references Legend: R = Readable bit - n = Value at POR reset Note: W = Writable bit '1' = Bit is set U = Unimplemented bit, read as `0' '0' = Bit is cleared x = Bit is unknown
On any device RESET, the port pins that are multiplexed with analog functions (ANx) are forced to be an analog input.
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The ADRESH:ADRESL registers contain the 10-bit result of the A/D conversion. When the A/D conversion is complete, the result is loaded into this A/D result register pair, the GO/DONE bit (ADCON0<2>) is cleared and the A/D interrupt flag bit ADIF is set. The block diagram of the A/D module is shown in Figure 11-1. After the A/D module has been configured as desired, the selected channel must be acquired before the conversion is started. The analog input channels must have their corresponding TRIS bits selected as inputs. To determine sample time, see Section 11.1. After this acquisition time has elapsed, the A/D conversion can be started. These steps should be followed for doing an A/D Conversion: 1. Configure the A/D module: * Configure analog pins/voltage reference and digital I/O (ADCON1) * Select A/D input channel (ADCON0) * Select A/D conversion clock (ADCON0) * Turn on A/D module (ADCON0) 6. 7. 2. Configure A/D interrupt (if desired): * Clear ADIF bit * Set ADIE bit * Set PEIE bit * Set GIE bit Wait the required acquisition time. Start conversion: * Set GO/DONE bit (ADCON0) Wait for A/D conversion to complete, by either: * Polling for the GO/DONE bit to be cleared (with interrupts enabled); OR * Waiting for the A/D interrupt Read A/D result register pair (ADRESH:ADRESL), clear bit ADIF, if required. For the next conversion, go to step 1 or step 2, as required. The A/D conversion time per bit is defined as TAD.
3. 4. 5.
FIGURE 11-1:
A/D BLOCK DIAGRAM
CHS2:CHS0
111 110 101 100
RE2/AN7(1) RE1/AN6(1) RE0/AN5(1) RA5/AN4
VAIN (Input Voltage) A/D Converter VDD
000 011 010
RA3/AN3/VREF+ RA2/AN2/VREF-
001
RA1/AN1 RA0/AN0
VREF+ (Reference Voltage) PCFG3:PCFG0 VREF(Reference Voltage) VSS PCFG3:PCFG0 Note 1: Not available on 28-pin devices.
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11.1 A/D Acquisition Requirements
For the A/D converter to meet its specified accuracy, the charge holding capacitor (CHOLD) must be allowed to fully charge to the input channel voltage level. The analog input model is shown in Figure 11-2. The source impedance (RS) and the internal sampling switch (RSS) impedance directly affect the time required to charge the capacitor CHOLD. The sampling switch (RSS) impedance varies over the device voltage (VDD), see Figure 11-2. The maximum recommended impedance for analog sources is 10 k. As the impedance is decreased, the acquisition time may be decreased. After the analog input channel is selected (changed), this acquisition must be done before the conversion can be started. To calculate the minimum acquisition time, Equation 11-1 may be used. This equation assumes that 1/2 LSb error is used (1024 steps for the A/D). The 1/2 LSb error is the maximum error allowed for the A/D to meet its specified resolution. To calculate the minimum acquisition time, TACQ, see the PICmicroTM Mid-Range Reference Manual (DS33023).
EQUATION 11-1:
TACQ
ACQUISITION TIME
= Amplifier Settling Time + Hold Capacitor Charging Time + Temperature Coefficient = = = = = = = TAMP + TC + TCOFF 2s + TC + [(Temperature -25C)(0.05s/C)] CHOLD (RIC + RSS + RS) In(1/2047) - 120pF (1k + 7k + 10k) In(0.0004885) 16.47s 2s + 16.47s + [(50C -25C)(0.05s/C) 19.72s
TC
TACQ
Note 1: The reference voltage (VREF) has no effect on the equation, since it cancels itself out. 2: The charge holding capacitor (CHOLD) is not discharged after each conversion. 3: The maximum recommended impedance for analog sources is 10 k. This is required to meet the pin leakage specification.
FIGURE 11-2:
ANALOG INPUT MODEL
VDD RS VA ANx CPIN 5 pF VT = 0.6V Sampling Switch RIC 1K SS RSS I LEAKAGE 500 nA CHOLD = DAC capacitance = 120 pF VSS
VT = 0.6V
Legend CPIN = input capacitance VT = threshold voltage I LEAKAGE = leakage current at the pin due to various junctions RIC = interconnect resistance SS = sampling switch CHOLD = sample/hold capacitance (from DAC)
6V 5V VDD 4V 3V 2V 5 6 7 8 9 10 11 Sampling Switch (k)
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11.2 Selecting the A/D Conversion Clock 11.3 Configuring Analog Port Pins
The ADCON1 and TRIS registers control the operation of the A/D port pins. The port pins that are desired as analog inputs, must have their corresponding TRIS bits set (input). If the TRIS bit is cleared (output), the digital output level (VOH or VOL) will be converted. The A/D operation is independent of the state of the CHS2:CHS0 bits and the TRIS bits. Note 1: When reading the port register, any pin configured as an analog input channel will read as cleared (a low level). Pins configured as digital inputs will convert an analog input. Analog levels on a digitally configured input will not affect the conversion accuracy. 2: Analog levels on any pin that is defined as a digital input (including the AN7:AN0 pins), may cause the input buffer to consume current that is out of the device specifications.
The A/D conversion time per bit is defined as TAD. The A/D conversion requires a minimum 12TAD per 10-bit conversion. The source of the A/D conversion clock is software selected. The seven possible options for TAD are: * * * * * * * 2TOSC 4TOSC 8TOSC 16TOSC 32TOSC 64TOSC Internal A/D module RC oscillator (2-6 s)
For correct A/D conversions, the A/D conversion clock (TAD) must be selected to ensure a minimum TAD time of 1.6 s. Table 11-1 shows the resultant TAD times derived from the device operating frequencies and the A/D clock source selected.
TABLE 11-1:
TAD vs. MAXIMUM DEVICE OPERATING FREQUENCIES (STANDARD DEVICES (C))
AD Clock Source (TAD) Maximum Device Frequency Max. 1.25 MHz 2.5 MHz 5 MHz 10 MHz 20 MHz 20 MHz (Note 1)
Operation 2TOSC 4TOSC 8TOSC 16TOSC 32TOSC 64TOSC RC
(1, 2, 3)
ADCS2:ADCS1:ADCS0 000 100 001 101 010 110 x11
Note 1: The RC source has a typical TAD time of 4 s, but can vary between 2-6 s. 2: When the device frequencies are greater than 1 MHz, the RC A/D conversion clock source is only recommended for SLEEP operation. 3: For extended voltage devices (LC), please refer to the Electrical Characteristics (Sections 17.1 and 17.2).
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11.4 A/D Conversions
Clearing the GO/DONE bit during a conversion will abort the current conversion. The A/D result register pair will NOT be updated with the partially completed A/D conversion sample. That is, the ADRESH:ADRESL registers will continue to contain the value of the last completed conversion (or the last value written to the ADRESH:ADRESL registers). After the A/D conversion is aborted, the next acquisition on the selected channel is automatically started. The GO/DONE bit can then be set to start the conversion. In Figure 11-3, after the GO bit is set, the first time segment has a minimum of TCY and a maximum of TAD. Note: The GO/DONE bit should NOT be set in the same instruction that turns on the A/D.
FIGURE 11-3:
A/D CONVERSION TAD CYCLES
TAD2 b9 Conversion starts TAD3 b8 TAD4 b7 TAD5 b6 TAD6 b5 TAD7 b4 TAD8 b3 TAD9 TAD10 TAD11 b2 b1 b0
TCY to TAD TAD1
Holding capacitor is disconnected from analog input (typically 100 ns) Set GO bit
ADRES is loaded GO bit is cleared ADIF bit is set Holding capacitor is connected to analog input
11.4.1
A/D RESULT REGISTERS
The ADRESH:ADRESL register pair is the location where the 10-bit A/D result is loaded at the completion of the A/D conversion. This register pair is 16-bits wide. The A/D module gives the flexibility to left or right justify the 10-bit result in the 16-bit result register. The A/D
Format Select bit (ADFM) controls this justification. Figure 11-4 shows the operation of the A/D result justification. The extra bits are loaded with '0's'. When an A/D result will not overwrite these locations (A/D disable), these registers may be used as two general purpose 8-bit registers.
FIGURE 11-4:
A/D RESULT JUSTIFICATION
10-bit Result ADFM = 1 ADFM = 0
7 0000 00
2107
0
7
0765 0000 00
0
ADRESH
ADRESL
ADRESH
ADRESL
10-bit Result Right Justified
10-bit Result Left Justified
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11.5 A/D Operation During SLEEP
Note: The A/D module can operate during SLEEP mode. This requires that the A/D clock source be set to RC (ADCS1:ADCS0 = 11). When the RC clock source is selected, the A/D module waits one instruction cycle before starting the conversion. This allows the SLEEP instruction to be executed, which eliminates all digital switching noise from the conversion. When the conversion is completed, the GO/DONE bit will be cleared and the result loaded into the ADRES register. If the A/D interrupt is enabled, the device will wake-up from SLEEP. If the A/D interrupt is not enabled, the A/D module will then be turned off, although the ADON bit will remain set. When the A/D clock source is another clock option (not RC), a SLEEP instruction will cause the present conversion to be aborted and the A/D module to be turned off, though the ADON bit will remain set. Turning off the A/D places the A/D module in its lowest current consumption state. For the A/D module to operate in SLEEP, the A/D clock source must be set to RC (ADCS1:ADCS0 = 11). To allow the conversion to occur during SLEEP, ensure the SLEEP instruction immediately follows the instruction that sets the GO/DONE bit.
11.6
Effects of a RESET
A device RESET forces all registers to their RESET state. This forces the A/D module to be turned off, and any conversion is aborted. All A/D input pins are configured as analog inputs. The value that is in the ADRESH:ADRESL registers is not modified for a Power-on Reset. The ADRESH:ADRESL registers will contain unknown data after a Power-on Reset.
TABLE 11-2:
Address
REGISTERS/BITS ASSOCIATED WITH A/D
Bit 7 GIE PSPIF(1) PSPIE
(1)
Name
Bit 6 PEIE ADIF ADIE
Bit 5 TMR0IE RCIF RCIE
Bit 4 INTE TXIF TXIE
Bit 3 RBIE SSPIF SSPIE
Bit 2 TMR0IF CCP1IF CCP1IE
Bit 1 INTF
Bit 0 RBIF
Value on POR, BOR
Value on MCLR, WDT
0Bh,8Bh, INTCON 10Bh,18Bh 0Ch 8Ch 1Eh 9Eh 1Fh 9Fh 85h 05h 89h(1) 09h
(1)
0000 000x 0000 000u
PIR1 PIE1
TMR2IF TMR1IF 0000 0000 0000 0000 TMR2IE TMR1IE 0000 0000 0000 0000
xxxx xxxx uuuu uuuu xxxx xxxx uuuu uuuu
ADRESH A/D Result Register High Byte ADRESL A/D Result Register Low Byte ADCON0 ADCON1 TRISA PORTA TRISE PORTE ADCS1 ADFM -- -- IBF -- ADCS0 ADCS2 -- -- OBF -- CHS2 -- CHS1 -- CHS0 PCFG3 GO/DONE PCFG2 -- PCFG1 ADON PCFG0
0000 00-0 0000 00-0 00-- 0000 00-- 0000
PORTA Data Direction Register PORTA Data Latch when written: PORTA pins when read IBOV -- PSPMODE -- -- -- PORTE Data Direction bits RE2 RE1 RE0
--11 1111 --11 1111 --0x 0000 --0u 0000 0000 -111 0000 -111 ---- -xxx ---- -uuu
Legend: x = unknown, u = unchanged, - = unimplemented, read as '0'. Shaded cells are not used for A/D conversion. Note 1: These registers are not available on 28-pin devices.
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NOTES:
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12.0 COMPARATOR MODULE
The comparator module contains two analog comparators. The inputs to the comparators are multiplexed with I/O port pins RA0 through RA3, while the outputs are multiplexed to pins RA4 and RA5. The on-chip Voltage Reference (Section 13.0) can also be an input to the comparators. The CMCON register (Register 12-1) controls the comparator input and output multiplexers. A block diagram of the various comparator configurations is shown in Figure 12-1.
REGISTER 12-1:
CMCON REGISTER
R-0 C2OUT bit 7 R-0 C1OUT R/W-0 C2INV R/W-0 C1INV R/W-0 CIS R/W-1 CM2 R/W-1 CM1 R/W-1 CM0 bit 0
bit 7
C2OUT: Comparator 2 Output bit When C2INV = 0: 1 = C2 VIN+ > C2 VIN- 0 = C2 VIN+ < C2 VIN- When C2INV = 1: 1 = C2 VIN+ < C2 VIN- 0 = C2 VIN+ > C2 VIN- C1OUT: Comparator 1 Output bit When C1INV = 0: 1 = C1 VIN+ > C1 VIN- 0 = C1 VIN+ < C1 VIN- When C1INV = 1: 1 = C1 VIN+ < C1 VIN- 0 = C1 VIN+ > C1 VIN- C2INV: Comparator 2 Output Inversion bit 1 = C2 output inverted 0 = C2 output not inverted C1INV: Comparator 1 Output Inversion bit 1 = C1 Output inverted 0 = C1 Output not inverted CIS: Comparator Input Switch bit When CM2:CM0 = 110: 1 = C1 VIN- connects to RA3/AN3 C2 VIN- connects to RA2/AN2 0 = C1 VIN- connects to RA0/AN0 C2 VIN- connects to RA1/AN1 CM2:CM0: Comparator Mode bits Figure 12-1 shows the Comparator modes and CM2:CM0 bit settings Legend: R = Readable bit - n = Value at POR W = Writable bit '1' = Bit is set U = Unimplemented bit, read as `0' '0' = Bit is cleared x = Bit is unknown
bit 6
bit 5
bit 4
bit 3
bit 2
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12.1 Comparator Configuration
There are eight modes of operation for the comparators. The CMCON register is used to select these modes. Figure 12-1 shows the eight possible modes. The TRISA register controls the data direction of the comparator pins for each mode. If the Comparator mode is changed, the comparator output level may not be valid for the specified mode change delay shown in the Electrical Specifications (Section 17.0). Note: Comparator interrupts should be disabled during a Comparator mode change. Otherwise, a false interrupt may occur.
FIGURE 12-1:
COMPARATOR I/O OPERATING MODES
Comparators Off CM2:CM0 = 111 RA0/AN0 C1 Off (Read as '0') RA3/AN3
D D VINVIN+
Comparators Reset (POR Default Value) CM2:CM0 = 000 RA0/AN0 RA3/AN3
A A VINVIN+
C1
Off (Read as '0')
RA1/AN1 RA2/AN2
A A
VINVIN+
RA1/AN1 C2 Off (Read as '0') RA2/AN2
D D
VINVIN+
C2
Off (Read as '0')
Two Independent Comparators CM2:CM0 = 010 RA0/AN0 RA3/AN3
A A VINVIN+
Two Independent Comparators with Outputs CM2:CM0 = 011 RA0/AN0
A A VINVIN+
C1
C1OUT
RA3/AN3
C1
C1OUT
RA4/T0CKI/C1OUT RA1/AN1 RA2/AN2
A A VINVIN+
C2
C2OUT
RA1/AN1 RA2/AN2
A A
VINVIN+
C2
C2OUT
RA5/SS/AN4/C2OUT Two Common Reference Comparators CM2:CM0 = 100 RA0/AN0 RA3/AN3
A A VINVIN+
Two Common Reference Comparators with Outputs CM2:CM0 = 101 RA0/AN0
A A VINVIN+
C1
C1OUT
RA3/AN3
C1
C1OUT
RA4/T0CKI/C1OUT RA1/AN1 RA2/AN2
A D VINVIN+
C2
C2OUT
RA1/AN1 RA2/AN2
A D
VINVIN+
C2
C2OUT
RA5/SS/AN4/C2OUT One Independent Comparator with Output CM2:CM0 = 001 RA0/AN0 RA3/AN3
A A VINVIN+
Four Inputs Multiplexed to Two Comparators CM2:CM0 = 110 RA0/AN0
A A CIS = 0 CIS = 1 VINVIN+ A A CIS = 0 CIS = 1 VINVIN+
C1
C1OUT
RA3/AN3 RA1/AN1 RA2/AN2
C1
C1OUT
RA4/T0CKI/C1OUT
D D
RA1/AN1 RA2/AN2
VINVIN+
C2
C2OUT
C2
Off (Read as '0') CVREF From Comparator VREF Module
A = Analog Input, port reads zeros always. D = Digital Input. CIS (CMCON<3>) is the Comparator Input Switch.
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12.2 Comparator Operation
12.3.2 INTERNAL REFERENCE SIGNAL
A single comparator is shown in Figure 12-2 along with the relationship between the analog input levels and the digital output. When the analog input at VIN+ is less than the analog input VIN-, the output of the comparator is a digital low level. When the analog input at VIN+ is greater than the analog input VIN-, the output of the comparator is a digital high level. The shaded areas of the output of the comparator in Figure 12-2 represent the uncertainty due to input offsets and response time. The comparator module also allows the selection of an internally generated voltage reference for the comparators. Section 13.0 contains a detailed description of the Comparator Voltage Reference Module that provides this signal. The internal reference signal is used when comparators are in mode CM<2:0> = 110 (Figure 12-1). In this mode, the internal voltage reference is applied to the VIN+ pin of both comparators.
12.4
Comparator Response Time
12.3
Comparator Reference
An external or internal reference signal may be used depending on the comparator operating mode. The analog signal present at VIN- is compared to the signal at VIN+, and the digital output of the comparator is adjusted accordingly (Figure 12-2).
Response time is the minimum time, after selecting a new reference voltage or input source, before the comparator output has a valid level. If the internal reference is changed, the maximum delay of the internal voltage reference must be considered when using the comparator outputs. Otherwise, the maximum delay of the comparators should be used (Section 17.0).
FIGURE 12-2:
SINGLE COMPARATOR
12.5
Comparator Outputs
VIN+ VIN-
+ -
Output
VIN- VIN- VIN+ VIN+
The comparator outputs are read through the CMCON Register. These bits are read only. The comparator outputs may also be directly output to the RA4 and RA5 I/O pins. When enabled, multiplexors in the output path of the RA4 and RA5 pins will switch and the output of each pin will be the unsynchronized output of the comparator. The uncertainty of each of the comparators is related to the input offset voltage and the response time given in the specifications. Figure 12-3 shows the comparator output block diagram. The TRISA bits will still function as an output enable/disable for the RA4 and RA5 pins while in this mode. The polarity of the comparator outputs can be changed using the C2INV and C1INV bits (CMCON<4:5>). Note 1: When reading the PORT register, all pins configured as analog inputs will read as a `0'. Pins configured as digital inputs will convert an analog input, according to the Schmitt Trigger input specification. 2: Analog levels on any pin defined as a digital input, may cause the input buffer to consume more current than is specified. 3: RA4 is an open collector I/O pin. When used as an output, a pull-up resistor is required.
Output utput
12.3.1
EXTERNAL REFERENCE SIGNAL
When external voltage references are used, the comparator module can be configured to have the comparators operate from the same, or different reference sources. However, threshold detector applications may require the same reference. The reference signal must be between VSS and VDD, and can be applied to either pin of the comparator(s).
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FIGURE 12-3: COMPARATOR OUTPUT BLOCK DIAGRAM
Port Pins
MULTIPLEX + CxINV
To RA4 or RA5 Pin Bus Data Read CMCON Q EN D
Set CMIF bit
Q From Other Comparator
D EN CL Read CMCON RESET
12.6
Comparator Interrupts
Note:
The comparator interrupt flag is set whenever there is a change in the output value of either comparator. Software will need to maintain information about the status of the output bits, as read from CMCON<7:6>, to determine the actual change that occurred. The CMIF bit (PIR registers) is the comparator interrupt flag. The CMIF bit must be RESET by clearing it (`0'). Since it is also possible to write a '1' to this register, a simulated interrupt may be initiated. The CMIE bit (PIE registers) and the PEIE bit (INTCON register) must be set to enable the interrupt. In addition, the GIE bit must also be set. If any of these bits are clear, the interrupt is not enabled, though the CMIF bit will still be set if an interrupt condition occurs.
If a change in the CMCON register (C1OUT or C2OUT) should occur when a read operation is being executed (start of the Q2 cycle), then the CMIF (PIR registers) interrupt flag may not get set.
The user, in the Interrupt Service Routine, can clear the interrupt in the following manner: a) b) Any read or write of CMCON will end the mismatch condition. Clear flag bit CMIF.
A mismatch condition will continue to set flag bit CMIF. Reading CMCON will end the mismatch condition, and allow flag bit CMIF to be cleared.
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12.7 Comparator Operation During SLEEP 12.9 Analog Input Connection Considerations
When a comparator is active and the device is placed in SLEEP mode, the comparator remains active and the interrupt is functional, if enabled. This interrupt will wake-up the device from SLEEP mode, when enabled. While the comparator is powered up, higher SLEEP currents than shown in the power-down current specification will occur. Each operational comparator will consume additional current, as shown in the comparator specifications. To minimize power consumption while in SLEEP mode, turn off the comparators, CM<2:0> = 111, before entering SLEEP. If the device wakes up from SLEEP, the contents of the CMCON register are not affected.
A simplified circuit for an analog input is shown in Figure 12-4. Since the analog pins are connected to a digital output, they have reverse biased diodes to VDD and VSS. The analog input, therefore, must be between VSS and VDD. If the input voltage deviates from this range by more than 0.6V in either direction, one of the diodes is forward biased and a latch-up condition may occur. A maximum source impedance of 10 k is recommended for the analog sources. Any external component connected to an analog input pin, such as a capacitor or a Zener diode, should have very little leakage current.
12.8
Effects of a RESET
A device RESET forces the CMCON register to its RESET state, causing the comparator module to be in the comparator off mode, CM<2:0> = 111. This ensures compatibility to the PIC16F87X devices.
FIGURE 12-4:
ANALOG INPUT MODEL
VDD RS < 10K AIN VT = 0.6 V RIC
VA
CPIN 5 pF
VT = 0.6 V
ILEAKAGE 500 nA
VSS Legend: CPIN VT ILEAKAGE RIC RS VA = = = = = = Input Capacitance Threshold Voltage Leakage Current at the pin due to various junctions Interconnect Resistance Source Impedance Analog Voltage
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TABLE 12-1:
Address 9Ch 9Dh
REGISTERS ASSOCIATED WITH COMPARATOR MODULE
Bit 7 C2OUT Bit 6 C1OUT CVROE PEIE/ GIEL CMIF CMIE -- -- Bit 5 C2INV CVRR TMR0IE -- -- RA5 Bit 4 C1INV -- INTIE -- -- RA4 Bit 3 CIS CVR3 RBIE BCLIF BCLIE RA3 Bit 2 CM2 CVR2 TMR0IF LVDIF LVDIE RA2 Bit 1 CM1 CVR1 INTIF Bit 0 CM0 CVR0 RBIF Value on POR Value on All Other RESETS
Name CMCON
0000 0111 0000 0111 000- 0000 000- 0000 0000 000x 0000 000u -0-- 0000 -0-- 0000
CVRCON CVREN GIE/ GIEH -- -- -- --
0Bh, 8Bh, INTCON 10Bh,18Bh 0Dh 8Dh 05h 85h PIR2 PIE2 PORTA TRISA
TMR3IF CCP2IF -0-- 0000 TMR3IE CCP2IE -0-- 0000 RA1 RA0
--0x 0000 --0u 0000 --11 1111 --11 1111
PORTA Data Direction Register
Legend: x = unknown, u = unchanged, - = unimplemented, read as "0". Shaded cells are unused by the comparator module.
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13.0 COMPARATOR VOLTAGE REFERENCE MODULE
supply voltage (also referred to as CVRSRC) comes directly from VDD. It should be noted, however, that the voltage at the top of the ladder is CVRSRC - VSAT, where VSAT is the saturation voltage of the power switch transistor. This reference will only be as accurate as the values of CVRSRC and VSAT. The output of the reference generator may be connected to the RA2/AN2/VREF-/CVREF pin. This can be used as a simple D/A function by the user, if a very high impedance load is used. The primary purpose of this function is to provide a test path for testing the reference generator function.
The Comparator Voltage Reference Generator is a 16-tap resistor ladder network that provides a fixed voltage reference when the comparators are in mode 110. A programmable register controls the function of the reference generator. Register 13-1 lists the bit functions of the CVRCON register. As shown in Figure 13-1, the resistor ladder is segmented to provide two ranges of CVREF values and has a power-down function to conserve power when the reference is not being used. The comparator reference
REGISTER 13-1:
CVRCON CONTROL REGISTER (ADDRESS 9Dh)
R/W-0 CVREN bit 7 R/W-0 CVROE R/W-0 CVRR U-0 -- R/W-0 CVR3 R/W-0 CVR2 R/W-0 CVR1 R/W-0 CVR0 bit 0
bit 7
CVREN: Comparator Voltage Reference Enable bit 1 = CVREF circuit powered on 0 = CVREF circuit powered down CVROE: Comparator VREF Output Enable bit 1 = CVREF voltage level is output on RA2/AN2/VREF-/CVREF pin 0 = CVREF voltage level is disconnected from RA2/AN2/VREF-/CVREF pin CVRR: Comparator VREF Range Selection bit 1 = 0 to 0.75 CVRSRC, with CVRSRC/24 step size 0 = 0.25 CVRSRC to 0.75 CVRSRC, with CVRSRC/32 step size Unimplemented: Read as `0' CVR3:CVR0: Comparator VREF Value Selection bits 0 VR3:VR0 15 When CVRR = 1: CVREF = (VR<3:0>/ 24) * (CVRSRC) When CVRR = 0: CVREF = 1/4 * (CVRSRC) + (VR3:VR0/ 32) * (CVRSRC) Legend: R = Readable bit -n = Value at POR W = Writable bit '1' = Bit is set U = Unimplemented bit, read as `0' '0' = Bit is cleared x = Bit is unknown
bit 6
bit 5
bit 4 bit 3-0
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PIC16F87XA
FIGURE 13-1: COMPARATOR VOLTAGE REFERENCE BLOCK DIAGRAM
VDD
16 Stages CVREN 8R R R R R
8R
CVRR
RA2/AN2/VREF-/CVREF
CVROE CVREF Input to Comparator 16:1 Analog MUX
CVR3 CVR2 CVR1 CVR0
TABLE 13-1:
Address 9Dh 9Ch
REGISTERS ASSOCIATED WITH COMPARATOR VOLTAGE REFERENCE
Bit 7 CVREN C2OUT Bit 6 CVROE C1OUT Bit 5 CVRR C2INV Bit 4 -- C1INV Bit 3 CVR3 CIS Bit 2 CVR2 CM2 Bit 1 CVR1 CM1 Bit 0 CVR0 CM0 Value On POR Value On All Other RESETS
Name CVRCON CMCON
000- 0000 000- 0000 0000 0111 0000 0111
Legend: x = unknown, u = unchanged, - = unimplemented, read as "0". Shaded cells are not used with the comparator voltage reference.
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14.0 SPECIAL FEATURES OF THE CPU
SLEEP mode is designed to offer a very low current Power-down mode. The user can wake-up from SLEEP through external RESET, Watchdog Timer Wake-up, or through an interrupt. Several oscillator options are also made available to allow the part to fit the application. The RC oscillator option saves system cost while the LP crystal option saves power. A set of configuration bits is used to select various options. Additional information on special features is available in the PICmicroTM Mid-Range Reference Manual, (DS33023).
All PIC16F87XA devices have a host of features intended to maximize system reliability, minimize cost through elimination of external components, provide power saving operating modes and offer code protection. These are: * Oscillator Selection * RESET - Power-on Reset (POR) - Power-up Timer (PWRT) - Oscillator Start-up Timer (OST) - Brown-out Reset (BOR) * Interrupts * Watchdog Timer (WDT) * SLEEP * Code Protection * ID Locations * In-Circuit Serial Programming * Low Voltage In-Circuit Serial Programming * In-Circuit Debugger PIC16F87XA devices have a Watchdog Timer, which can be shut-off only through configuration bits. It runs off its own RC oscillator for added reliability. There are two timers that offer necessary delays on power-up. One is the Oscillator Start-up Timer (OST), intended to keep the chip in RESET until the crystal oscillator is stable. The other is the Power-up Timer (PWRT), which provides a fixed delay of 72 ms (nominal) on power-up only. It is designed to keep the part in RESET while the power supply stabilizes. With these two timers on-chip, most applications need no external RESET circuitry.
14.1
Configuration Bits
The configuration bits can be programmed (read as '0'), or left unprogrammed (read as '1'), to select various device configurations. The erased, or unprogrammed value of the configuration word is 3FFFh. These bits are mapped in program memory location 2007h. It is important to note that address 2007h is beyond the user program memory space, which can be accessed only during programming.
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PIC16F87XA
REGISTER 14-1:
R/P-1 CP bit13 bit 13 CP: FLASH Program Memory Code Protection bit 1 = Code protection off 0 = All program memory code protected Unimplemented: Read as `1' DEBUG: In-Circuit Debugger Mode bit 1 = In-Circuit Debugger disabled, RB6 and RB7 are general purpose I/O pins 0 = In-Circuit Debugger enabled, RB6 and RB7 are dedicated to the debugger WRT1:WRT0 FLASH Program Memory Write Enable bits For PIC16F876A/877A: 11 = Write protection off; all program memory may be written to by EECON control 10 = 0000h to 00FFh write protected; 0100h to 1FFFh may be written to by EECON control 01 = 0000h to 07FFh write protected; 0800h to 1FFFh may be written to by EECON control 00 = 0000h to 0FFFh write protected; 1000h to 1FFFh may be written to by EECON control For PIC16F873A/874A: 11 = Write protection off; all program memory may be written to by EECON control 10 = 0000h to 00FFh write protected; 0100h to 0FFFh may be written to by EECON control 01 = 0000h to 03FFh write protected; 0400h to 0FFFh may be written to by EECON control 00 = 0000h to 07FFh write protected; 0800h to 0FFFh may be written to by EECON control bit 8 CPD: Data EEPROM Memory Code Protection bit 1 = Data EEPROM code protection off 0 = Data EEPROM code protected LVP: Low Voltage In-Circuit Serial Programming Enable bit 1 = RB3/PGM pin has PGM function; low voltage programming enabled 0 = RB3 is digital I/O, HV on MCLR must be used for programming BOREN: Brown-out Reset Enable bit 1 = BOR enabled 0 = BOR disabled Unimplemented: Read as `1' PWRTEN: Power-up Timer Enable bit 1 = PWRT disabled 0 = PWRT enabled WDTEN: Watchdog Timer Enable bit 1 = WDT enabled 0 = WDT disabled FOSC1:FOSC0: Oscillator Selection bits 11 = RC oscillator 10 = HS oscillator 01 = XT oscillator 00 = LP oscillator Note 1: The erased (unprogrammed) value of the configuration word is 3FFFh. U-0 -- R/P-1 DEBUG
CONFIGURATION WORD (ADDRESS 2007h)(1)
R/P-1 WRT1 R/P-1 WRT0 R/P-1 CPD R/P-1 LVP R/P-1 BOREN U-0 -- U-0 -- R/P-1 PWRTEN R/P-1 WDTEN R/P-1 F0SC1 R/P-1 F0SC0 bit0
bit 12 bit 11
bit 10-9
bit 7
bit 6
bit 5-4 bit 3
bit 2
bit 1-0
Legend: R = Readable bit - n = Value when device is unprogrammed P = Programmable bit U = Unimplemented bit, read as `0' u = Unchanged from programmed state
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14.2
14.2.1
Oscillator Configurations
OSCILLATOR TYPES
FIGURE 14-2:
The PIC16F87XA can be operated in four different oscillator modes. The user can program two configuration bits (FOSC1 and FOSC0) to select one of these four modes: * * * * LP XT HS RC Low Power Crystal Crystal/Resonator High Speed Crystal/Resonator Resistor/Capacitor
EXTERNAL CLOCK INPUT OPERATION (HS, XT OR LP OSC CONFIGURATION)
Clock from Ext. System
Open
OSC1 PIC16F87XA OSC2
14.2.2
CRYSTAL OSCILLATOR/CERAMIC RESONATORS TABLE 14-1: CERAMIC RESONATORS
Ranges Tested: Mode XT Freq. 455 kHz 2.0 MHz 4.0 MHz 8.0 MHz 16.0 MHz OSC1 68 - 100 pF 15 - 68 pF 15 - 68 pF 10 - 68 pF 10 - 22 pF OSC2 68 - 100 pF 15 - 68 pF 15 - 68 pF 10 - 68 pF 10 - 22 pF
In XT, LP or HS modes, a crystal or ceramic resonator is connected to the OSC1/CLKIN and OSC2/CLKOUT pins to establish oscillation (Figure 14-1). The PIC16F87XA oscillator design requires the use of a parallel cut crystal. Use of a series cut crystal may give a frequency out of the crystal manufacturers specifications. When in XT, LP or HS modes, the device can have an external clock source to drive the OSC1/ CLKIN pin (Figure 14-2).
HS
FIGURE 14-1:
CRYSTAL/CERAMIC RESONATOR OPERATION (HS, XT OR LP OSC CONFIGURATION)
OSC1 To Internal Logic SLEEP PIC16F87XA
These values are for design guidance only. See notes following Table 14-2. Resonators Used: 455 kHz 2.0 MHz 4.0 MHz 8.0 MHz 16.0 MHz Panasonic EFO-A455K04B Murata Erie CSA2.00MG Murata Erie CSA4.00MG Murata Erie CSA8.00MT Murata Erie CSA16.00MX 0.3% 0.5% 0.5% 0.5% 0.5%
C1(1)
XTAL OSC2 C2(1) Rs(2)
RF(3)
All resonators used did not have built-in capacitors.
Note 1: See Table 14-1 and Table 14-2 for recommended values of C1 and C2. 2: A series resistor (Rs) may be required for AT strip cut crystals. 3: RF varies with the crystal chosen.
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TABLE 14-2: CAPACITOR SELECTION FOR CRYSTAL OSCILLATOR
Cap. Range C1 33 pF 15 pF 47-68 pF 15 pF 15 pF 15 pF 15-33 pF 15-33 pF Cap. Range C2 33 pF 15 pF 47-68 pF 15 pF 15 pF 15 pF 15-33 pF 15-33 pF
14.2.3
RC OSCILLATOR
Osc Type LP XT
Crystal Freq. 32 kHz 200 kHz 200 kHz 1 MHz 4 MHz
HS
4 MHz 8 MHz 20 MHz
For timing insensitive applications, the "RC" device option offers additional cost savings. The RC oscillator frequency is a function of the supply voltage, the resistor (REXT) and capacitor (CEXT) values, and the operating temperature. In addition to this, the oscillator frequency will vary from unit to unit due to normal process parameter variation. Furthermore, the difference in lead frame capacitance between package types will also affect the oscillation frequency, especially for low CEXT values. The user also needs to take into account variation due to tolerance of external R and C components used. Figure 14-3 shows how the R/C combination is connected to the PIC16F87XA.
These values are for design guidance only. See notes following this table. Crystals Used 32 kHz 200 kHz 1 MHz 4 MHz 8 MHz 20 MHz Epson C-001R32.768K-A STD XTL 200.000KHz ECS ECS-10-13-1 ECS ECS-40-20-1 EPSON CA-301 8.000M-C EPSON CA-301 20.000M-C 20 PPM 20 PPM 50 PPM 50 PPM 30 PPM 30 PPM
FIGURE 14-3:
VDD REXT
RC OSCILLATOR MODE
OSC1 CEXT VSS FOSC/4 OSC2/CLKOUT
Internal Clock PIC16F87XA
Recommended values:
3 k REXT 100 k CEXT > 20pF
Note 1: Higher capacitance increases the stability of oscillator, but also increases the startup time. 2: Since each resonator/crystal has its own characteristics, the user should consult the resonator/crystal manufacturer for appropriate values of external components. 3: Rs may be required in HS mode, as well as XT mode, to avoid overdriving crystals with low drive level specification. 4: When migrating from other PICmicro(R) devices, oscillator performance should be verified.
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14.3 RESET
The PIC16F87XA differentiates between various kinds of RESET: * * * * * * Power-on Reset (POR) MCLR Reset during normal operation MCLR Reset during SLEEP WDT Reset (during normal operation) WDT Wake-up (during SLEEP) Brown-out Reset (BOR) "RESET state" on Power-on Reset (POR), on the MCLR and WDT Reset, on MCLR Reset during SLEEP, and Brown-out Reset (BOR). They are not affected by a WDT Wake-up, which is viewed as the resumption of normal operation. The TO and PD bits are set or cleared differently in different RESET situations, as indicated in Table 14-4. These bits are used in software to determine the nature of the RESET. See Table 14-6 for a full description of RESET states of all registers. A simplified block diagram of the On-Chip Reset Circuit is shown in Figure 14-4.
Some registers are not affected in any RESET condition. Their status is unknown on POR and unchanged in any other RESET. Most other registers are reset to a
FIGURE 14-4:
SIMPLIFIED BLOCK DIAGRAM OF ON-CHIP RESET CIRCUIT
External Reset
MCLR WDT Module VDD Rise Detect VDD Brown-out Reset OST/PWRT OST Chip_Reset 10-bit Ripple Counter OSC1 (1) On-chip RC OSC PWRT 10-bit Ripple Counter R Q Power-on Reset S WDT SLEEP
Time-out Reset
BODEN
Enable PWRT Enable OST Note 1: This is a separate oscillator from the RC oscillator of the CLKIN pin.
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14.4 MCLR 14.6 Power-up Timer (PWRT)
PIC16F87XA devices have a noise filter in the MCLR Reset path. The filter will detect and ignore small pulses. It should be noted that a WDT Reset does not drive MCLR pin low. The behavior of the ESD protection on the MCLR pin differs from previous devices of this family. Voltages applied to the pin that exceed its specification can result in both RESETS and current consumption outside of device specification during the RESET event. For this reason, Microchip recommends that the MCLR pin no longer be tied directly to VDD. The use of an RC network, as shown in Figure 14-5, is suggested. The Power-up Timer provides a fixed 72 ms nominal time-out on power-up only from the POR. The Powerup Timer operates on an internal RC oscillator. The chip is kept in RESET as long as the PWRT is active. The PWRT's time delay allows VDD to rise to an acceptable level. A configuration bit is provided to enable or disable the PWRT. The power-up time delay will vary from chip to chip due to VDD, temperature and process variation. See Section 17.0 for details (TPWRT, parameter #33).
14.7
Oscillator Start-up Timer (OST)
FIGURE 14-5:
RECOMMENDED MCLR CIRCUIT
PIC16F87XA
The Oscillator Start-up Timer (OST) provides a delay of 1024 oscillator cycles (from OSC1 input) after the PWRT delay is over (if PWRT is enabled). This helps to ensure that the crystal oscillator or resonator has started and stabilized. The OST time-out is invoked only for XT, LP and HS modes and only on Power-on Reset or Wake-up from SLEEP.
VDD
R1 1 k (or greater) MCLR C1 0.1 F (not critical)
14.8
Brown-out Reset (BOR)
The configuration bit, BODEN, can enable or disable the Brown-out Reset circuit. If VDD falls below VBOR (parameter D005, about 4V) for longer than TBOR (parameter #35, about 100 S), the brown-out situation will reset the device. If VDD falls below VBOR for less than TBOR, a RESET may not occur. Once the brown-out occurs, the device will remain in Brown-out Reset until VDD rises above VBOR. The Power-up Timer then keeps the device in RESET for TPWRT (parameter #33, about 72 mS). If VDD should fall below VBOR during TPWRT, the Brown-out Reset process will restart when VDD rises above VBOR with the Power-up Timer Reset. The Power-up Timer is always enabled when the Brown-out Reset circuit is enabled, regardless of the state of the PWRT configuration bit.
14.5
Power-On Reset (POR)
A Power-on Reset pulse is generated on-chip when VDD rise is detected (in the range of 1.2V - 1.7V). To take advantage of the POR, tie the MCLR pin to VDD through an RC network, as described in Section 14.4. A maximum rise time for VDD is specified. See Section 17.0 ("Electrical Specifications") for details. When the device starts normal operation (exits the RESET condition), device operating parameters (voltage, frequency, temperature, etc.) must be met to ensure operation. If these conditions are not met, the device must be held in RESET until the operating conditions are met. Brown-out Reset may be used to meet the start-up conditions. For additional information, refer to Application Note, AN007, "Power-up Trouble Shooting", (DS00007).
14.9
Time-out Sequence
On power-up, the time-out sequence is as follows: the PWRT delay starts (if enabled) when a POR Reset occurs. Then, OST starts counting 1024 oscillator cycles when PWRT ends (LP, XT, HS). When the OST ends, the device comes out of RESET. If MCLR is kept low long enough, the time-outs will expire. Bringing MCLR high will begin execution immediately. This is useful for testing purposes or to synchronize more than one PIC16F87XA device operating in parallel. Table 14-5 shows the RESET conditions for the STATUS, PCON and PC registers, while Table 14-6 shows the RESET conditions for all the registers.
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14.10 Power Control/Status Register (PCON)
The Power Control/Status Register, PCON, has up to two bits depending upon the device. Bit0 is the Brown-out Reset Status bit, BOR. The BOR bit is unknown on a Power-on Reset. It must then be set by the user and checked on subsequent RESETS to see if it has been cleared, indicating that a BOR has occurred. When the Brown-out Reset is disabled, the state of the BOR bit is unpredictable and is, therefore, not valid at any time. Bit1 is POR (Power-on Reset Status bit). It is cleared on a Power-on Reset and unaffected otherwise. The user must set this bit following a Power-on Reset.
TABLE 14-3:
TIME-OUT IN VARIOUS SITUATIONS
Power-up Brown-out PWRTE = 0 PWRTE = 1 1024TOSC -- 72 ms + 1024TOSC 72 ms 72 ms + 1024TOSC 72 ms Wake-up from SLEEP 1024TOSC --
Oscillator Configuration XT, HS, LP RC
TABLE 14-4:
POR 0 0 0 1 1 1 1 1 BOR x x x 0 1 1 1 1
STATUS BITS AND THEIR SIGNIFICANCE
TO 1 0 x 1 0 0 u 1 PD 1 x 0 1 1 0 u 0 Power-on Reset Illegal, TO is set on POR Illegal, PD is set on POR Brown-out Reset WDT Reset WDT Wake-up MCLR Reset during normal operation MCLR Reset during SLEEP or interrupt wake-up from SLEEP
Legend: x = don't care, u = unchanged
TABLE 14-5:
RESET CONDITION FOR SPECIAL REGISTERS
Condition Program Counter 000h 000h 000h 000h PC + 1 000h PC + 1(1) STATUS Register 0001 1xxx 000u uuuu 0001 0uuu 0000 1uuu uuu0 0uuu 0001 1uuu uuu1 0uuu PCON Register ---- --0x ---- --uu ---- --uu ---- --uu ---- --uu ---- --u0 ---- --uu
Power-on Reset MCLR Reset during normal operation MCLR Reset during SLEEP WDT Reset WDT Wake-up Brown-out Reset Interrupt wake-up from SLEEP
Legend: u = unchanged, x = unknown, - = unimplemented bit, read as '0' Note 1: When the wake-up is due to an interrupt and the GIE bit is set, the PC is loaded with the interrupt vector (0004h).
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TABLE 14-6:
Register W INDF TMR0 PCL STATUS FSR PORTA PORTB PORTC PORTD PORTE PCLATH INTCON PIR1
INITIALIZATION CONDITIONS FOR ALL REGISTERS
Devices Power-on Reset, Brown-out Reset MCLR Resets, WDT Reset Wake-up via WDT or Interrupt
73A 74A 76A 77A xxxx xxxx uuuu uuuu uuuu uuuu 73A 74A 76A 77A N/A N/A N/A 73A 74A 76A 77A xxxx xxxx uuuu uuuu uuuu uuuu 73A 74A 76A 77A 0000 0000 0000 0000 PC + 1(2) (3) 73A 74A 76A 77A 0001 1xxx 000q quuu uuuq quuu(3) 73A 74A 76A 77A xxxx xxxx uuuu uuuu uuuu uuuu 73A 74A 76A 77A --0x 0000 --0u 0000 --uu uuuu 73A 74A 76A 77A xxxx xxxx uuuu uuuu uuuu uuuu 73A 74A 76A 77A xxxx xxxx uuuu uuuu uuuu uuuu 73A 74A 76A 77A xxxx xxxx uuuu uuuu uuuu uuuu 73A 74A 76A 77A ---- -xxx ---- -uuu ---- -uuu 73A 74A 76A 77A ---0 0000 ---0 0000 ---u uuuu 73A 74A 76A 77A 0000 000x 0000 000u uuuu uuuu(1) 73A 74A 76A 77A r000 0000 r000 0000 ruuu uuuu(1) 73A 74A 76A 77A 0000 0000 0000 0000 uuuu uuuu(1) PIR2 73A 74A 76A 77A -0-0 0--0 -0-0 0--0 -u-u u--u(1) TMR1L 73A 74A 76A 77A xxxx xxxx uuuu uuuu uuuu uuuu TMR1H 73A 74A 76A 77A xxxx xxxx uuuu uuuu uuuu uuuu T1CON 73A 74A 76A 77A --00 0000 --uu uuuu --uu uuuu TMR2 73A 74A 76A 77A 0000 0000 0000 0000 uuuu uuuu T2CON 73A 74A 76A 77A -000 0000 -000 0000 -uuu uuuu SSPBUF 73A 74A 76A 77A xxxx xxxx uuuu uuuu uuuu uuuu SSPCON 73A 74A 76A 77A 0000 0000 0000 0000 uuuu uuuu CCPR1L 73A 74A 76A 77A xxxx xxxx uuuu uuuu uuuu uuuu CCPR1H 73A 74A 76A 77A xxxx xxxx uuuu uuuu uuuu uuuu CCP1CON 73A 74A 76A 77A --00 0000 --00 0000 --uu uuuu RCSTA 73A 74A 76A 77A 0000 000x 0000 000x uuuu uuuu TXREG 73A 74A 76A 77A 0000 0000 0000 0000 uuuu uuuu RCREG 73A 74A 76A 77A 0000 0000 0000 0000 uuuu uuuu CCPR2L 73A 74A 76A 77A xxxx xxxx uuuu uuuu uuuu uuuu CCPR2H 73A 74A 76A 77A xxxx xxxx uuuu uuuu uuuu uuuu CCP2CON 73A 74A 76A 77A 0000 0000 0000 0000 uuuu uuuu ADRESH 73A 74A 76A 77A xxxx xxxx uuuu uuuu uuuu uuuu ADCON0 73A 74A 76A 77A 0000 00-0 0000 00-0 uuuu uu-u OPTION_REG 73A 74A 76A 77A 1111 1111 1111 1111 uuuu uuuu TRISA 73A 74A 76A 77A --11 1111 --11 1111 --uu uuuu TRISB 73A 74A 76A 77A 1111 1111 1111 1111 uuuu uuuu TRISC 73A 74A 76A 77A 1111 1111 1111 1111 uuuu uuuu TRISD 73A 74A 76A 77A 1111 1111 1111 1111 uuuu uuuu TRISE 73A 74A 76A 77A 0000 -111 0000 -111 uuuu -uuu Legend: u = unchanged, x = unknown, - = unimplemented bit, read as '0', q = value depends on condition, r = reserved, maintain clear. Shaded cells indicate conditions do not apply for the designated device. Note 1: One or more bits in INTCON, PIR1 and/or PIR2 will be affected (to cause wake-up). 2: When the wake-up is due to an interrupt and the GIE bit is set, the PC is loaded with the interrupt vector (0004h). 3: See Table 14-5 for RESET value for specific condition.
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TABLE 14-6:
Register PIE1
INITIALIZATION CONDITIONS FOR ALL REGISTERS (CONTINUED)
Devices Power-on Reset, Brown-out Reset MCLR Resets, WDT Reset Wake-up via WDT or Interrupt
73A 74A 76A 77A r000 0000 r000 0000 ruuu uuuu 73A 74A 76A 77A 0000 0000 0000 0000 uuuu uuuu PIE2 73A 74A 76A 77A -0-0 0--0 -0-0 0--0 -u-u u--u PCON 73A 74A 76A 77A ---- --qq ---- --uu ---- --uu SSPCON2 73A 74A 76A 77A 0000 0000 0000 0000 uuuu uuuu PR2 73A 74A 76A 77A 1111 1111 1111 1111 1111 1111 SSPADD 73A 74A 76A 77A 0000 0000 0000 0000 uuuu uuuu SSPSTAT 73A 74A 76A 77A --00 0000 --00 0000 --uu uuuu TXSTA 73A 74A 76A 77A 0000 -010 0000 -010 uuuu -uuu SPBRG 73A 74A 76A 77A 0000 0000 0000 0000 uuuu uuuu CMCON 73A 974 76A 77A 0000 0111 0000 0111 uuuu uuuu CVRCON 73A 74A 76A 77A 000- 0000 000- 0000 uuu- uuuu ADRESL 73A 74A 76A 77A xxxx xxxx uuuu uuuu uuuu uuuu ADCON1 73A 74A 76A 77A 00-- 0000 00-- 0000 uu-- uuuu EEDATA 73A 74A 76A 77A 0--- 0000 0--- 0000 u--- uuuu EEADR 73A 74A 76A 77A xxxx xxxx uuuu uuuu uuuu uuuu EEDATH 73A 74A 76A 77A xxxx xxxx uuuu uuuu uuuu uuuu EEADRH 73A 74A 76A 77A xxxx xxxx uuuu uuuu uuuu uuuu EECON1 73A 74A 76A 77A x--- x000 u--- u000 u--- uuuu EECON2 73A 74A 76A 77A ---- ------- ------- ---Legend: u = unchanged, x = unknown, - = unimplemented bit, read as '0', q = value depends on condition, r = reserved, maintain clear. Shaded cells indicate conditions do not apply for the designated device. Note 1: One or more bits in INTCON, PIR1 and/or PIR2 will be affected (to cause wake-up). 2: When the wake-up is due to an interrupt and the GIE bit is set, the PC is loaded with the interrupt vector (0004h). 3: See Table 14-5 for RESET value for specific condition.
FIGURE 14-6:
TIME-OUT SEQUENCE ON POWER-UP (MCLR TIED TO VDD VIA RC NETWORK)
VDD
MCLR INTERNAL POR TPWRT
PWRT TIME-OUT
TOST
OST TIME-OUT
INTERNAL RESET
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FIGURE 14-7: TIME-OUT SEQUENCE ON POWER-UP (MCLR NOT TIED TO VDD): CASE 1
VDD
MCLR INTERNAL POR TPWRT
PWRT TIME-OUT
TOST
OST TIME-OUT
INTERNAL RESET
FIGURE 14-8:
TIME-OUT SEQUENCE ON POWER-UP (MCLR NOT TIED TO VDD): CASE 2
VDD
MCLR INTERNAL POR TPWRT
PWRT TIME-OUT
TOST
OST TIME-OUT
INTERNAL RESET
FIGURE 14-9:
SLOW RISE TIME (MCLR TIED TO VDD VIA RC NETWORK)
5V VDD MCLR 0V 1V
INTERNAL POR TPWRT PWRT TIME-OUT TOST OST TIME-OUT INTERNAL RESET
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14.11 Interrupts
The PIC16F87XA family has up to 15 sources of interrupt. The interrupt control register (INTCON) records individual interrupt requests in flag bits. It also has individual and global interrupt enable bits. Note: Individual interrupt flag bits are set, regardless of the status of their corresponding mask bit, or the GIE bit. The RB0/INT pin interrupt, the RB port change interrupt, and the TMR0 overflow interrupt flags are contained in the INTCON register. The peripheral interrupt flags are contained in the special function registers, PIR1 and PIR2. The corresponding interrupt enable bits are contained in special function registers, PIE1 and PIE2, and the peripheral interrupt enable bit is contained in special function register INTCON. When an interrupt is responded to, the GIE bit is cleared to disable any further interrupt, the return address is pushed onto the stack and the PC is loaded with 0004h. Once in the Interrupt Service Routine, the source(s) of the interrupt can be determined by polling the interrupt flag bits. The interrupt flag bit(s) must be cleared in software before re-enabling interrupts to avoid recursive interrupts. For external interrupt events, such as the INT pin or PORTB change interrupt, the interrupt latency will be three or four instruction cycles. The exact latency depends when the interrupt event occurs. The latency is the same for one or two-cycle instructions. Individual interrupt flag bits are set, regardless of the status of their corresponding mask bit, PEIE bit, or GIE bit.
A global interrupt enable bit, GIE (INTCON<7>) enables (if set) all unmasked interrupts, or disables (if cleared) all interrupts. When bit GIE is enabled, and an interrupt's flag bit and mask bit are set, the interrupt will vector immediately. Individual interrupts can be disabled through their corresponding enable bits in various registers. Individual interrupt bits are set, regardless of the status of the GIE bit. The GIE bit is cleared on RESET. The "return from interrupt" instruction, RETFIE, exits the interrupt routine, as well as sets the GIE bit, which re-enables interrupts.
FIGURE 14-10:
EEIF EEIE PSPIF(1) PSPIE(1) ADIF ADIE RCIF RCIE
INTERRUPT LOGIC
TMR0IF TMR0IE TXIF TXIE SSPIF SSPIE CCP1IF CCP1IE TMR2IF TMR2IE INTF INTE RBIF RBIE PEIE GIE
Wake-up (If in SLEEP mode)
Interrupt to CPU
TMR1IF TMR1IE CCP2IF CCP2IE BCLIF BCLIE CMIF CMIE Note 1: PSP interrupt is implemented only on PIC16F874A/877A devices.
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14.11.1 INT INTERRUPT
14.12 Context Saving During Interrupts
During an interrupt, only the return PC value is saved on the stack. Typically, users may wish to save key registers during an interrupt, (i.e., W register and STATUS register). This will have to be implemented in software. For the PIC16F873A/874A devices, the register W_TEMP must be defined in both banks 0 and 1 and must be defined at the same offset from the bank base address (i.e., If W_TEMP is defined at 0x20 in bank 0, it must also be defined at 0xA0 in bank 1). The registers, PCLATH_TEMP and STATUS_TEMP, are only defined in bank 0. Since the upper 16 bytes of each bank are common in the PIC16F876A/877A devices, temporary holding registers W_TEMP, STATUS_TEMP, and PCLATH_TEMP should be placed in here. These 16 locations don't require banking and therefore, make it easier for context save and restore. The same code shown in Example 14-1 can be used.
External interrupt on the RB0/INT pin is edge triggered, either rising, if bit INTEDG (OPTION_REG<6>) is set, or falling, if the INTEDG bit is clear. When a valid edge appears on the RB0/INT pin, flag bit INTF (INTCON<1>) is set. This interrupt can be disabled by clearing enable bit INTE (INTCON<4>). Flag bit INTF must be cleared in software in the Interrupt Service Routine before re-enabling this interrupt. The INT interrupt can wake-up the processor from SLEEP, if bit INTE was set prior to going into SLEEP. The status of global interrupt enable bit, GIE, decides whether or not the processor branches to the interrupt vector following wake-up. See Section 14.14 for details on SLEEP mode.
14.11.2
TMR0 INTERRUPT
An overflow (FFh 00h) in the TMR0 register will set flag bit TMR0IF (INTCON<2>). The interrupt can be enabled/disabled by setting/clearing enable bit TMR0IE (INTCON<5>) (Section 5.0).
14.11.3
PORTB INTCON CHANGE
An input change on PORTB<7:4> sets flag bit RBIF (INTCON<0>). The interrupt can be enabled/disabled by setting/clearing enable bit RBIE (INTCON<4>) (Section 4.2).
EXAMPLE 14-1:
MOVWF SWAPF CLRF MOVWF MOVF MOVWF CLRF : :(ISR) : MOVF MOVWF SWAPF MOVWF SWAPF SWAPF
SAVING STATUS, W, AND PCLATH REGISTERS IN RAM
;Copy ;Swap ;bank ;Save ;Only ;Save ;Page W to TEMP register status to be saved into W 0, regardless of current bank, Clears IRP,RP1,RP0 status to bank zero STATUS_TEMP register required if using pages 1, 2 and/or 3 PCLATH into W zero, regardless of current page
W_TEMP STATUS,W STATUS STATUS_TEMP PCLATH, W PCLATH_TEMP PCLATH
;(Insert user code here) PCLATH_TEMP, W PCLATH STATUS_TEMP,W STATUS W_TEMP,F W_TEMP,W ;Restore PCLATH ;Move W into PCLATH ;Swap STATUS_TEMP register into W ;(sets bank to original state) ;Move W into STATUS register ;Swap W_TEMP ;Swap W_TEMP into W
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14.13 Watchdog Timer (WDT)
The Watchdog Timer is a free running on-chip RC oscillator, which does not require any external components. This RC oscillator is separate from the RC oscillator of the OSC1/CLKIN pin. That means that the WDT will run, even if the clock on the OSC1/CLKIN and OSC2/ CLKOUT pins of the device has been stopped, for example, by execution of a SLEEP instruction. During normal operation, a WDT time-out generates a device RESET (Watchdog Timer Reset). If the device is in SLEEP mode, a WDT time-out causes the device to wake-up and continue with normal operation (Watchdog Timer Wake-up). The TO bit in the STATUS register will be cleared upon a Watchdog Timer time-out. The WDT can be permanently disabled by clearing configuration bit WDTE (Section 14.1). WDT time-out period values may be found in the Electrical Specifications section under parameter #31. Values for the WDT prescaler (actually a postscaler, but shared with the Timer0 prescaler) may be assigned using the OPTION_REG register. Note 1: The CLRWDT and SLEEP instructions clear the WDT and the postscaler, if assigned to the WDT, and prevent it from timing out and generating a device RESET condition. 2: When a CLRWDT instruction is executed and the prescaler is assigned to the WDT, the prescaler count will be cleared, but the prescaler assignment is not changed.
FIGURE 14-11:
WATCHDOG TIMER BLOCK DIAGRAM
From TMR0 Clock Source (Figure 5-1) 0 WDT Timer 1 M U X
Postscaler 8 8 - to - 1 MUX PS2:PS0
WDT Enable Bit
PSA To TMR0 (Figure 5-1) 0 MUX 1 PSA
WDT Time-out Note: PSA and PS2:PS0 are bits in the OPTION_REG register.
TABLE 14-7:
Address 2007h 81h,181h
SUMMARY OF WATCHDOG TIMER REGISTERS
Name Bit 7 (1) RBPU Bit 6 BODEN(1) INTEDG Bit 5 CP1 T0CS Bit 4 CP0 T0SE Bit 3 PWRTE(1) PSA Bit 2 WDTE PS2 Bit 1 FOSC1 PS1 Bit 0 FOSC0 PS0
Config. bits OPTION_REG
Legend: Shaded cells are not used by the Watchdog Timer. Note 1: See Register 14-1 for operation of these bits.
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14.14 Power-down Mode (SLEEP)
Power-down mode is entered by executing a SLEEP instruction. If enabled, the Watchdog Timer will be cleared but keeps running, the PD bit (STATUS<3>) is cleared, the TO (STATUS<4>) bit is set, and the oscillator driver is turned off. The I/O ports maintain the status they had before the SLEEP instruction was executed (driving high, low, or hi-impedance). For lowest current consumption in this mode, place all I/O pins at either VDD or VSS, ensure no external circuitry is drawing current from the I/O pin, power-down the A/D and disable external clocks. Pull all I/O pins that are hi-impedance inputs, high or low externally, to avoid switching currents caused by floating inputs. The T0CKI input should also be at VDD or VSS for lowest current consumption. The contribution from on-chip pull-ups on PORTB should also be considered. The MCLR pin must be at a logic high level (VIHMC). When the SLEEP instruction is being executed, the next instruction (PC + 1) is pre-fetched. For the device to wake-up through an interrupt event, the corresponding interrupt enable bit must be set (enabled). Wake-up is regardless of the state of the GIE bit. If the GIE bit is clear (disabled), the device continues execution at the instruction after the SLEEP instruction. If the GIE bit is set (enabled), the device executes the instruction after the SLEEP instruction and then branches to the interrupt address (0004h). In cases where the execution of the instruction following SLEEP is not desirable, the user should have a NOP after the SLEEP instruction.
14.14.2
WAKE-UP USING INTERRUPTS
When global interrupts are disabled (GIE cleared) and any interrupt source has both its interrupt enable bit and interrupt flag bit set, one of the following will occur: * If the interrupt occurs before the execution of a SLEEP instruction, the SLEEP instruction will complete as a NOP. Therefore, the WDT and WDT postscaler will not be cleared, the TO bit will not be set and PD bits will not be cleared. * If the interrupt occurs during or after the execution of a SLEEP instruction, the device will immediately wake-up from SLEEP. The SLEEP instruction will be completely executed before the wake-up. Therefore, the WDT and WDT postscaler will be cleared, the TO bit will be set and the PD bit will be cleared. Even if the flag bits were checked before executing a SLEEP instruction, it may be possible for flag bits to become set before the SLEEP instruction completes. To determine whether a SLEEP instruction executed, test the PD bit. If the PD bit is set, the SLEEP instruction was executed as a NOP. To ensure that the WDT is cleared, a CLRWDT instruction should be executed before a SLEEP instruction.
14.14.1
WAKE-UP FROM SLEEP
The device can wake-up from SLEEP through one of the following events: 1. 2. 3. External RESET input on MCLR pin. Watchdog Timer Wake-up (if WDT was enabled). Interrupt from INT pin, RB port change or peripheral interrupt.
External MCLR Reset will cause a device RESET. All other events are considered a continuation of program execution and cause a "wake-up". The TO and PD bits in the STATUS register can be used to determine the cause of device RESET. The PD bit, which is set on power-up, is cleared when SLEEP is invoked. The TO bit is cleared if a WDT time-out occurred and caused wake-up. The following peripheral interrupts can wake the device from SLEEP: PSP read or write (PIC16F874/877 only). TMR1 interrupt. Timer1 must be operating as an asynchronous counter. 3. CCP Capture mode interrupt. 4. Special event trigger (Timer1 in Asynchronous mode using an external clock). 5. SSP (START/STOP) bit detect interrupt. 6. SSP transmit or receive in Slave mode (SPI/I2C). 7. USART RX or TX (Synchronous Slave mode). 8. A/D conversion (when A/D clock source is RC). 9. EEPROM write operation completion. 10. Comparator output changes state. Other peripherals cannot generate interrupts since during SLEEP, no on-chip clocks are present. 1. 2.
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FIGURE 14-12:
OSC1 CLKOUT(4) INT pin INTF Flag (INTCON<1>) GIE bit (INTCON<7>) INSTRUCTION FLOW PC Instruction Fetched Instruction Executed PC Inst(PC) = SLEEP Inst(PC - 1) PC+1 Inst(PC + 1) SLEEP PC+2 PC+2 Inst(PC + 2) Inst(PC + 1) Dummy cycle PC + 2 0004h Inst(0004h) Dummy cycle 0005h Inst(0005h) Inst(0004h) Processor in SLEEP Interrupt Latency(2) TOST(2)
WAKE-UP FROM SLEEP THROUGH INTERRUPT
Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4
Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1
Note 1: XT, HS or LP oscillator mode assumed. 2: TOST = 1024TOSC (drawing not to scale) This delay will not be there for RC osc mode. 3: GIE = '1' assumed. In this case, after wake- up, the processor jumps to the interrupt routine. If GIE = '0', execution will continue in-line. 4: CLKOUT is not available in these osc modes, but shown here for timing reference.
14.15 In-Circuit Debugger
When the DEBUG bit in the configuration word is programmed to a '0', the In-Circuit Debugger functionality is enabled. This function allows simple debugging functions when used with MPLAB(R) ICD. When the microcontroller has this feature enabled, some of the resources are not available for general use. Table 14-8 shows which features are consumed by the background debugger.
14.16 Program Verification/Code Protection
If the code protection bit(s) have not been programmed, the on-chip program memory can be read out for verification purposes.
14.17 ID Locations
Four memory locations (2000h - 2003h) are designated as ID locations, where the user can store checksum or other code identification numbers. These locations are not accessible during normal execution, but are readable and writable during program/verify. It is recommended that only the 4 Least Significant bits of the ID location are used.
TABLE 14-8:
I/O pins Stack
DEBUGGER RESOURCES
RB6, RB7 1 level Address 0000h must be NOP Last 100h words 0x070 (0x0F0, 0x170, 0x1F0) 0x1EB - 0x1EF
Program Memory Data Memory
To use the In-Circuit Debugger function of the microcontroller, the design must implement In-Circuit Serial Programming connections to MCLR/VPP, VDD, GND, RB7 and RB6. This will interface to the In-Circuit Debugger module available from Microchip, or one of the third party development tool companies.
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14.18 In-Circuit Serial Programming
PIC16F87XA microcontrollers can be serially programmed while in the end application circuit. This is simply done with two lines for clock and data and three other lines for power, ground, and the programming voltage. This allows customers to manufacture boards with unprogrammed devices, and then program the microcontroller just before shipping the product. This also allows the most recent firmware, or a custom firmware to be programmed. When using ICSP, the part must be supplied at 4.5V to 5.5V, if a bulk erase will be executed. This includes reprogramming of the code protect, both from an onstate to off-state. For all other cases of ICSP, the part may be programmed at the normal operating voltages. This means calibration values, unique user IDs, or user code can be reprogrammed or added. For complete details of serial programming, please refer to the EEPROM Memory Programming Specification for the PIC16F87XA. Note 1: The High Voltage Programming mode is always available, regardless of the state of the LVP bit, by applying VIHH to the MCLR pin. 2: While in Low Voltage ICSP mode, the RB3 pin can no longer be used as a general purpose I/O pin. 3: When using low voltage ICSP programming (LVP) and the pull-ups on PORTB are enabled, bit 3 in the TRISB register must be cleared to disable the pull-up on RB3 and ensure the proper operation of the device. 4: RB3 should not be allowed to float if LVP is enabled. An external pull-down device should be used to default the device to normal operating mode. If RB3 floats high, the PIC16F87XA device will enter Programming mode. 5: LVP mode is enabled by default on all devices shipped from Microchip. It can be disabled by clearing the LVP bit in the CONFIG register. 6: Disabling LVP will provide maximum compatibility to other PIC16CXXX devices. If Low Voltage Programming mode is not used, the LVP bit can be programmed to a '0' and RB3/PGM becomes a digital I/O pin. However, the LVP bit may only be programmed when programming is entered with VIHH on MCLR. The LVP bit can only be charged when using high voltage on MCLR. It should be noted, that once the LVP bit is programmed to 0, only the High Voltage Programming mode is available and only High Voltage Programming mode can be used to program the device. When using low voltage ICSP, the part must be supplied at 4.5V to 5.5V, if a bulk erase will be executed. This includes reprogramming of the code protect bits from an on-state to off-state. For all other cases of low voltage ICSP, the part may be programmed at the normal operating voltage. This means calibration values, unique user IDs, or user code can be reprogrammed or added.
14.19 Low Voltage ICSP Programming
The LVP bit of the configuration word enables low voltage ICSP programming. This mode allows the microcontroller to be programmed via ICSP using a VDD source in the operating voltage range. This only means that VPP does not have to be brought to VIHH, but can instead be left at the normal operating voltage. In this mode, the RB3/PGM pin is dedicated to the programming function and ceases to be a general purpose I/O pin. During programming, VDD is applied to the MCLR pin. To enter Programming mode, VDD must be applied to the RB3/PGM, provided the LVP bit is set. The LVP bit defaults to on (`1') from the factory.
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15.0 INSTRUCTION SET SUMMARY
The PIC16 instruction set is highly orthogonal and is comprised of three basic categories: * Byte-oriented operations * Bit-oriented operations * Literal and control operations Each PIC16 instruction is a 14-bit word divided into an opcode which specifies the instruction type, and one or more operands which further specify the operation of the instruction. The formats for each of the categories is presented in Figure 15-1, while the various opcode fields are summarized in Table 15-1. Table 13-2 lists the instructions recognized by the MPASMTM Assembler. A complete description of each instruction is also available in the PICmicroTM MidRange Reference Manual (DS33023). For byte-oriented instructions, `f' represents a file register designator and `d' represents a destination designator. The file register designator specifies which file register is to be used by the instruction. The destination designator specifies where the result of the operation is to be placed. If `d' is zero, the result is placed in the W register. If `d' is one, the result is placed in the file register specified in the instruction. For bit-oriented instructions, `b' represents a bit field designator which selects the bit affected by the operation, while `f' represents the address of the file in which the bit is located. For literal and control operations, `k' represents an eight- or eleven-bit constant or literal value One instruction cycle consists of four oscillator periods; for an oscillator frequency of 4 MHz, this gives a normal instruction execution time of 1 s. All instructions are executed within a single instruction cycle, unless a conditional test is true or the program counter is changed as a result of an instruction. When this occurs, the execution takes two instruction cycles with the second cycle executed as a NOP. Note: To maintain upward compatibility with future PIC16F87XA products, do not use the OPTION and TRIS instructions. For example, a "clrf PORTB" instruction will read PORTB, clear all the data bits, then write the result back to PORTB. This example would have the unintended result that the condition that sets the RBIF flag would be cleared.
TABLE 15-1:
Field
f W b k x
OPCODE FIELD DESCRIPTIONS
Description
Register file address (0x00 to 0x7F) Working register (accumulator) Bit address within an 8-bit file register Literal field, constant data or label Don't care location (= 0 or 1). The assembler will generate code with x = 0. It is the recommended form of use for compatibility with all Microchip software tools. Destination select; d = 0: store result in W, d = 1: store result in file register f. Default is d = 1. Program Counter Time-out bit Power-down bit
d
PC TO PD
FIGURE 15-1:
GENERAL FORMAT FOR INSTRUCTIONS
0
Byte-oriented file register operations 13 876 OPCODE d f (FILE #) d = 0 for destination W d = 1 for destination f f = 7-bit file register address Bit-oriented file register operations 13 10 9 76 OPCODE b (BIT #) f (FILE #) b = 3-bit bit address f = 7-bit file register address Literal and control operations General 13 OPCODE k = 8-bit immediate value CALL and GOTO instructions only 13 11 OPCODE 10 k (literal) 8 7 k (literal)
0
All instruction examples use the format `0xhh' to represent a hexadecimal number, where `h' signifies a hexadecimal digit.
0
15.1
READ-MODIFY-WRITE OPERATIONS
Any instruction that specifies a file register as part of the instruction performs a Read-Modify-Write (R-M-W) operation. The register is read, the data is modified, and the result is stored according to either the instruction or the destination designator `d'. A read operation is performed on a register even if the instruction writes to that register.
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0
k = 11-bit immediate value
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TABLE 15-2:
Mnemonic, Operands
PIC16F87XA INSTRUCTION SET
14-Bit Opcode Description Cycles MSb BYTE-ORIENTED FILE REGISTER OPERATIONS LSb Status Affected Notes
ADDWF ANDWF CLRF CLRW COMF DECF DECFSZ INCF INCFSZ IORWF MOVF MOVWF NOP RLF RRF SUBWF SWAPF XORWF
f, d f, d f f, d f, d f, d f, d f, d f, d f, d f f, d f, d f, d f, d f, d
Add W and f AND W with f Clear f Clear W Complement f Decrement f Decrement f, Skip if 0 Increment f Increment f, Skip if 0 Inclusive OR W with f Move f Move W to f No Operation Rotate Left f through Carry Rotate Right f through Carry Subtract W from f Swap nibbles in f Exclusive OR W with f
1 1 1 1 1 1 1(2) 1 1(2) 1 1 1 1 1 1 1 1 1
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
0111 0101 0001 0001 1001 0011 1011 1010 1111 0100 1000 0000 0000 1101 1100 0010 1110 0110
dfff dfff lfff 0xxx dfff dfff dfff dfff dfff dfff dfff lfff 0xx0 dfff dfff dfff dfff dfff
ffff ffff ffff xxxx ffff ffff ffff ffff ffff ffff ffff ffff 0000 ffff ffff ffff ffff ffff
C,DC,Z Z Z Z Z Z Z Z Z
1,2 1,2 2 1,2 1,2 1,2,3 1,2 1,2,3 1,2 1,2
C C C,DC,Z Z
1,2 1,2 1,2 1,2 1,2
BIT-ORIENTED FILE REGISTER OPERATIONS BCF BSF BTFSC BTFSS ADDLW ANDLW CALL CLRWDT GOTO IORLW MOVLW RETFIE RETLW RETURN SLEEP SUBLW XORLW f, b f, b f, b f, b k k k k k k k k k Bit Clear f Bit Set f Bit Test f, Skip if Clear Bit Test f, Skip if Set Add literal and W AND literal with W Call subroutine Clear Watchdog Timer Go to address Inclusive OR literal with W Move literal to W Return from interrupt Return with literal in W Return from Subroutine Go into Standby mode Subtract W from literal Exclusive OR literal with W 1 1 1 (2) 1 (2) 1 1 2 1 2 1 1 2 2 2 1 1 1
01 01 01 01 11 11 10 00 10 11 11 00 11 00 00 11 11 00bb 01bb 10bb 11bb 111x 1001 0kkk 0000 1kkk 1000 00xx 0000 01xx 0000 0000 110x 1010 bfff bfff bfff bfff kkkk kkkk kkkk 0110 kkkk kkkk kkkk 0000 kkkk 0000 0110 kkkk kkkk ffff ffff ffff ffff kkkk kkkk kkkk 0100 kkkk kkkk kkkk 1001 kkkk 1000 0011 kkkk kkkk
1,2 1,2 3 3 C,DC,Z Z TO,PD Z
LITERAL AND CONTROL OPERATIONS
TO,PD C,DC,Z Z
Note 1: When an I/O register is modified as a function of itself ( e.g., MOVF PORTB, 1), the value used will be that value present on the pins themselves. For example, if the data latch is '1' for a pin configured as input and is driven low by an external device, the data will be written back with a '0'. 2: If this instruction is executed on the TMR0 register (and, where applicable, d = 1), the prescaler will be cleared if assigned to the Timer0 module. 3: If Program Counter (PC) is modified, or a conditional test is true, the instruction requires two cycles. The second cycle is executed as a NOP.
Note:
Additional information on the mid-range instruction set is available in the PICmicroTM Mid-Range MCU Family Reference Manual (DS33023).
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15.2
ADDLW Syntax: Operands: Operation: Status Affected: Description:
Instruction Descriptions
Add Literal and W [ label ] ADDLW 0 k 255 (W) + k (W) C, DC, Z The contents of the W register are added to the eight-bit literal 'k' and the result is placed in the W register. Operation: Status Affected: Description: k BCF Syntax: Operands: Bit Clear f [ label ] BCF 0 f 127 0b7 0 (f) None Bit 'b' in register 'f' is cleared. f,b
ADDWF Syntax: Operands: Operation: Status Affected: Description:
Add W and f [ label ] ADDWF 0 f 127 d [0,1] (W) + (f) (destination) C, DC, Z Add the contents of the W register with register 'f'. If 'd' is 0, the result is stored in the W register. If 'd' is 1, the result is stored back in register 'f'. f,d
BSF Syntax: Operands: Operation: Status Affected: Description:
Bit Set f [ label ] BSF 0 f 127 0b7 1 (f) None Bit 'b' in register 'f' is set. f,b
ANDLW Syntax: Operands: Operation: Status Affected: Description:
AND Literal with W [ label ] ANDLW 0 k 255 (W) .AND. (k) (W) Z The contents of W register are AND'ed with the eight-bit literal 'k'. The result is placed in the W register. k
BTFSS Syntax: Operands: Operation: Status Affected: Description:
Bit Test f, Skip if Set [ label ] BTFSS f,b 0 f 127 0b<7 skip if (f) = 1 None If bit 'b' in register 'f' is '0', the next instruction is executed. If bit 'b' is '1', then the next instruction is discarded and a NOP is executed instead, making this a 2TCY instruction.
ANDWF Syntax: Operands: Operation: Status Affected: Description:
AND W with f [ label ] ANDWF 0 f 127 d [0,1] (W) .AND. (f) (destination) Z AND the W register with register 'f'. If 'd' is 0, the result is stored in the W register. If 'd' is 1, the result is stored back in register 'f'. f,d
BTFSC Syntax: Operands: Operation: Status Affected: Description:
Bit Test, Skip if Clear [ label ] BTFSC f,b 0 f 127 0b7 skip if (f) = 0 None If bit 'b' in register 'f' is '1', the next instruction is executed. If bit 'b', in register 'f', is '0', the next instruction is discarded, and a NOP is executed instead, making this a 2TCY instruction.
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CALL Syntax: Operands: Operation: Call Subroutine [ label ] CALL k 0 k 2047 (PC)+ 1 TOS, k PC<10:0>, (PCLATH<4:3>) PC<12:11> None Call Subroutine. First, return address (PC+1) is pushed onto the stack. The eleven-bit immediate address is loaded into PC bits <10:0>. The upper bits of the PC are loaded from PCLATH. CALL is a two-cycle instruction. Status Affected: Description: CLRWDT Syntax: Operands: Operation: Clear Watchdog Timer [ label ] CLRWDT None 00h WDT 0 WDT prescaler, 1 TO 1 PD TO, PD CLRWDT instruction resets the Watchdog Timer. It also resets the prescaler of the WDT. Status bits TO and PD are set.
Status Affected: Description:
CLRF Syntax: Operands: Operation: Status Affected: Description:
Clear f [ label ] CLRF 0 f 127 00h (f) 1Z Z The contents of register 'f' are cleared and the Z bit is set. f
COMF Syntax: Operands: Operation: Status Affected: Description:
Complement f [ label ] COMF 0 f 127 d [0,1] (f) (destination) Z The contents of register 'f' are complemented. If 'd' is 0, the result is stored in W. If 'd' is 1, the result is stored back in register 'f'. f,d
CLRW Syntax: Operands: Operation: Status Affected: Description:
Clear W [ label ] CLRW None 00h (W) 1Z Z W register is cleared. Zero bit (Z) is set.
DECF Syntax: Operands: Operation: Status Affected: Description:
Decrement f [ label ] DECF f,d 0 f 127 d [0,1] (f) - 1 (destination) Z Decrement register 'f'. If 'd' is 0, the result is stored in the W register. If 'd' is 1, the result is stored back in register 'f'.
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DECFSZ Syntax: Operands: Operation: Status Affected: Description: Decrement f, Skip if 0 [ label ] DECFSZ f,d 0 f 127 d [0,1] (f) - 1 (destination); skip if result = 0 None The contents of register 'f' are decremented. If 'd' is 0, the result is placed in the W register. If 'd' is 1, the result is placed back in register 'f'. If the result is 1, the next instruction is executed. If the result is 0, then a NOP is executed instead, making it a 2TCY instruction. INCFSZ Syntax: Operands: Operation: Status Affected: Description: Increment f, Skip if 0 [ label ] INCFSZ f,d 0 f 127 d [0,1] (f) + 1 (destination), skip if result = 0 None The contents of register 'f' are incremented. If 'd' is 0, the result is placed in the W register. If 'd' is 1, the result is placed back in register 'f'. If the result is 1, the next instruction is executed. If the result is 0, a NOP is executed instead, making it a 2TCY instruction.
GOTO Syntax: Operands: Operation: Status Affected: Description:
Unconditional Branch [ label ] GOTO k 0 k 2047 k PC<10:0> PCLATH<4:3> PC<12:11> None GOTO is an unconditional branch. The eleven-bit immediate value is loaded into PC bits <10:0>. The upper bits of PC are loaded from PCLATH<4:3>. GOTO is a twocycle instruction.
IORLW Syntax: Operands: Operation: Status Affected: Description:
Inclusive OR Literal with W [ label ] IORLW k 0 k 255 (W) .OR. k (W) Z The contents of the W register are OR'ed with the eight-bit literal 'k'. The result is placed in the W register.
INCF Syntax: Operands: Operation: Status Affected: Description:
Increment f [ label ] INCF f,d 0 f 127 d [0,1] (f) + 1 (destination) Z The contents of register 'f' are incremented. If 'd' is 0, the result is placed in the W register. If 'd' is 1, the result is placed back in register 'f'.
IORWF Syntax: Operands: Operation: Status Affected: Description:
Inclusive OR W with f [ label ] IORWF f,d 0 f 127 d [0,1] (W) .OR. (f) (destination) Z Inclusive OR the W register with register 'f'. If 'd' is 0 the result is placed in the W register. If 'd' is 1 the result is placed back in register 'f'.
2001 Microchip Technology Inc.
Advance Information
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PIC16F87XA
MOVF Syntax: Operands: Operation: Status Affected: Description: Move f [ label ] MOVF f,d 0 f 127 d [0,1] (f) (destination) Z The contents of register f are moved to a destination dependant upon the status of d. If d = 0, destination is W register. If d = 1, the destination is file register f itself. d = 1 is useful to test a file register, since status flag Z is affected. NOP Syntax: Operands: Operation: Status Affected: Description: No Operation [ label ] None No operation None No operation. NOP
MOVLW Syntax: Operands: Operation: Status Affected: Description:
Move Literal to W [ label ] k (W) None The eight-bit literal 'k' is loaded into W register. The don't cares will assemble as 0's. MOVLW k 0 k 255
RETFIE Syntax: Operands: Operation: Status Affected:
Return from Interrupt [ label ] None TOS PC, 1 GIE None RETFIE
MOVWF Syntax: Operands: Operation: Status Affected: Description:
Move W to f [ label ] (W) (f) None Move data from W register to register 'f'. MOVWF f 0 f 127
RETLW Syntax: Operands: Operation: Status Affected: Description:
Return with Literal in W [ label ] RETLW k 0 k 255 k (W); TOS PC None The W register is loaded with the eight-bit literal 'k'. The program counter is loaded from the top of the stack (the return address). This is a two-cycle instruction.
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PIC16F87XA
RLF Syntax: Operands: Operation: Status Affected: Description: Rotate Left f through Carry [ label ] RLF 0 f 127 d [0,1] See description below C The contents of register 'f' are rotated one bit to the left through the Carry Flag. If 'd' is 0, the result is placed in the W register. If 'd' is 1, the result is stored back in register 'f'.
C Register f
SLEEP Syntax: Operands: Operation: [ label ] SLEEP None 00h WDT, 0 WDT prescaler, 1 TO, 0 PD TO, PD The power-down status bit, PD is cleared. Time-out status bit, TO is set. Watchdog Timer and its prescaler are cleared. The processor is put into SLEEP mode with the oscillator stopped.
f,d
Status Affected: Description:
RETURN Syntax: Operands: Operation: Status Affected: Description:
Return from Subroutine [ label ] None TOS PC None Return from subroutine. The stack is POPed and the top of the stack (TOS) is loaded into the program counter. This is a two-cycle instruction. RETURN
SUBLW Syntax: Operands: Operation: Description:
Subtract W from Literal [ label ] SUBLW k 0 k 255 k - (W) (W) The W register is subtracted (2's complement method) from the eight-bit literal 'k'. The result is placed in the W register.
Status Affected: C, DC, Z
RRF Syntax: Operands: Operation: Status Affected: Description:
Rotate Right f through Carry [ label ] RRF f,d 0 f 127 d [0,1] See description below C The contents of register 'f' are rotated one bit to the right through the Carry Flag. If 'd' is 0, the result is placed in the W register. If 'd' is 1, the result is placed back in register 'f'.
C Register f
SUBWF Syntax: Operands: Operation: Status Affected: Description:
Subtract W from f [ label ] SUBWF f,d 0 f 127 d [0,1] (f) - (W) (destination) C, DC, Z Subtract (2's complement method) W register from register 'f'. If 'd' is 0, the result is stored in the W register. If 'd' is 1, the result is stored back in register 'f'.
2001 Microchip Technology Inc.
Advance Information
DS39582A-page 163
PIC16F87XA
SWAPF Syntax: Operands: Operation: Swap Nibbles in f [ label ] SWAPF f,d 0 f 127 d [0,1] (f<3:0>) (destination<7:4>), (f<7:4>) (destination<3:0>) The upper and lower nibbles of register 'f' are exchanged. If 'd' is 0, the result is placed in the W register. If 'd' is 1, the result is placed in register 'f'. XORWF Syntax: Operands: Operation: Status Affected: Description: Exclusive OR W with f [ label ] XORWF 0 f 127 d [0,1] (W) .XOR. (f) (destination) Z Exclusive OR the contents of the W register with register 'f'. If 'd' is 0, the result is stored in the W register. If 'd' is 1, the result is stored back in register 'f'. f,d
Status Affected: None Description:
XORLW Syntax: Operands: Operation: Status Affected: Description:
Exclusive OR Literal with W [ label ] XORLW k 0 k 255 (W) .XOR. k (W) Z The contents of the W register are XOR'ed with the eight-bit literal 'k'. The result is placed in the W register.
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PIC16F87XA
16.0 DEVELOPMENT SUPPORT
The MPLAB IDE allows you to: * Edit your source files (either assembly or `C') * One touch assemble (or compile) and download to PICmicro emulator and simulator tools (automatically updates all project information) * Debug using: - source files - absolute listing file - machine code The ability to use MPLAB IDE with multiple debugging tools allows users to easily switch from the costeffective simulator to a full-featured emulator with minimal retraining. The PICmicro(R) microcontrollers are supported with a full range of hardware and software development tools: * Integrated Development Environment - MPLAB(R) IDE Software * Assemblers/Compilers/Linkers - MPASMTM Assembler - MPLAB C17 and MPLAB C18 C Compilers - MPLINKTM Object Linker/ MPLIBTM Object Librarian * Simulators - MPLAB SIM Software Simulator * Emulators - MPLAB ICE 2000 In-Circuit Emulator - ICEPICTM In-Circuit Emulator * In-Circuit Debugger - MPLAB ICD * Device Programmers - PRO MATE(R) II Universal Device Programmer - PICSTART(R) Plus Entry-Level Development Programmer * Low Cost Demonstration Boards - PICDEMTM 1 Demonstration Board - PICDEM 2 Demonstration Board - PICDEM 3 Demonstration Board - PICDEM 17 Demonstration Board - KEELOQ(R) Demonstration Board
16.2
MPASM Assembler
The MPASM assembler is a full-featured universal macro assembler for all PICmicro MCU's. The MPASM assembler has a command line interface and a Windows shell. It can be used as a stand-alone application on a Windows 3.x or greater system, or it can be used through MPLAB IDE. The MPASM assembler generates relocatable object files for the MPLINK object linker, Intel(R) standard HEX files, MAP files to detail memory usage and symbol reference, an absolute LST file that contains source lines and generated machine code, and a COD file for debugging. The MPASM assembler features include: * Integration into MPLAB IDE projects. * User-defined macros to streamline assembly code. * Conditional assembly for multi-purpose source files. * Directives that allow complete control over the assembly process.
16.1
MPLAB Integrated Development Environment Software
The MPLAB IDE software brings an ease of software development previously unseen in the 8-bit microcontroller market. The MPLAB IDE is a Windows(R)-based application that contains: * An interface to debugging tools - simulator - programmer (sold separately) - emulator (sold separately) - in-circuit debugger (sold separately) * A full-featured editor * A project manager * Customizable toolbar and key mapping * A status bar * On-line help
16.3
MPLAB C17 and MPLAB C18 C Compilers
The MPLAB C17 and MPLAB C18 Code Development Systems are complete ANSI `C' compilers for Microchip's PIC17CXXX and PIC18CXXX family of microcontrollers, respectively. These compilers provide powerful integration capabilities and ease of use not found with other compilers. For easier source level debugging, the compilers provide symbol information that is compatible with the MPLAB IDE memory display.
2001 Microchip Technology Inc.
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DS39582A-page 165
PIC16F87XA
16.4 MPLINK Object Linker/ MPLIB Object Librarian 16.6 MPLAB ICE High Performance Universal In-Circuit Emulator with MPLAB IDE
The MPLINK object linker combines relocatable objects created by the MPASM assembler and the MPLAB C17 and MPLAB C18 C compilers. It can also link relocatable objects from pre-compiled libraries, using directives from a linker script. The MPLIB object librarian is a librarian for precompiled code to be used with the MPLINK object linker. When a routine from a library is called from another source file, only the modules that contain that routine will be linked in with the application. This allows large libraries to be used efficiently in many different applications. The MPLIB object librarian manages the creation and modification of library files. The MPLINK object linker features include: * Integration with MPASM assembler and MPLAB C17 and MPLAB C18 C compilers. * Allows all memory areas to be defined as sections to provide link-time flexibility. The MPLIB object librarian features include: * Easier linking because single libraries can be included instead of many smaller files. * Helps keep code maintainable by grouping related modules together. * Allows libraries to be created and modules to be added, listed, replaced, deleted or extracted.
The MPLAB ICE universal in-circuit emulator is intended to provide the product development engineer with a complete microcontroller design tool set for PICmicro microcontrollers (MCUs). Software control of the MPLAB ICE in-circuit emulator is provided by the MPLAB Integrated Development Environment (IDE), which allows editing, building, downloading and source debugging from a single environment. The MPLAB ICE 2000 is a full-featured emulator system with enhanced trace, trigger and data monitoring features. Interchangeable processor modules allow the system to be easily reconfigured for emulation of different processors. The universal architecture of the MPLAB ICE in-circuit emulator allows expansion to support new PICmicro microcontrollers. The MPLAB ICE in-circuit emulator system has been designed as a real-time emulation system, with advanced features that are generally found on more expensive development tools. The PC platform and Microsoft(R) Windows environment were chosen to best make these features available to you, the end user.
16.7
ICEPIC In-Circuit Emulator
16.5
MPLAB SIM Software Simulator
The MPLAB SIM software simulator allows code development in a PC-hosted environment by simulating the PICmicro series microcontrollers on an instruction level. On any given instruction, the data areas can be examined or modified and stimuli can be applied from a file, or user-defined key press, to any of the pins. The execution can be performed in single step, execute until break, or trace mode. The MPLAB SIM simulator fully supports symbolic debugging using the MPLAB C17 and the MPLAB C18 C compilers and the MPASM assembler. The software simulator offers the flexibility to develop and debug code outside of the laboratory environment, making it an excellent multiproject software development tool.
The ICEPIC low cost, in-circuit emulator is a solution for the Microchip Technology PIC16C5X, PIC16C6X, PIC16C7X and PIC16CXXX families of 8-bit OneTime-Programmable (OTP) microcontrollers. The modular system can support different subsets of PIC16C5X or PIC16CXXX products through the use of interchangeable personality modules, or daughter boards. The emulator is capable of emulating without target application circuitry being present.
DS39582A-page 166
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PIC16F87XA
16.8 MPLAB ICD In-Circuit Debugger
Microchip's In-Circuit Debugger, MPLAB ICD, is a powerful, low cost, run-time development tool. This tool is based on the FLASH PICmicro MCUs and can be used to develop for this and other PICmicro microcontrollers. The MPLAB ICD utilizes the in-circuit debugging capability built into the FLASH devices. This feature, along with Microchip's In-Circuit Serial ProgrammingTM protocol, offers cost-effective in-circuit FLASH debugging from the graphical user interface of the MPLAB Integrated Development Environment. This enables a designer to develop and debug source code by watching variables, single-stepping and setting break points. Running at full speed enables testing hardware in realtime.
16.11 PICDEM 1 Low Cost PICmicro Demonstration Board
The PICDEM 1 demonstration board is a simple board which demonstrates the capabilities of several of Microchip's microcontrollers. The microcontrollers supported are: PIC16C5X (PIC16C54 to PIC16C58A), PIC16C61, PIC16C62X, PIC16C71, PIC16C8X, PIC17C42, PIC17C43 and PIC17C44. All necessary hardware and software is included to run basic demo programs. The user can program the sample microcontrollers provided with the PICDEM 1 demonstration board on a PRO MATE II device programmer, or a PICSTART Plus development programmer, and easily test firmware. The user can also connect the PICDEM 1 demonstration board to the MPLAB ICE incircuit emulator and download the firmware to the emulator for testing. A prototype area is available for the user to build some additional hardware and connect it to the microcontroller socket(s). Some of the features include an RS-232 interface, a potentiometer for simulated analog input, push button switches and eight LEDs connected to PORTB.
16.9
PRO MATE II Universal Device Programmer
The PRO MATE II universal device programmer is a full-featured programmer, capable of operating in stand-alone mode, as well as PC-hosted mode. The PRO MATE II device programmer is CE compliant. The PRO MATE II device programmer has programmable VDD and VPP supplies, which allow it to verify programmed memory at VDD min and VDD max for maximum reliability. It has an LCD display for instructions and error messages, keys to enter commands and a modular detachable socket assembly to support various package types. In stand-alone mode, the PRO MATE II device programmer can read, verify, or program PICmicro devices. It can also set code protection in this mode.
16.12 PICDEM 2 Low Cost PIC16CXX Demonstration Board
The PICDEM 2 demonstration board is a simple demonstration board that supports the PIC16C62, PIC16C64, PIC16C65, PIC16C73 and PIC16C74 microcontrollers. All the necessary hardware and software is included to run the basic demonstration programs. The user can program the sample microcontrollers provided with the PICDEM 2 demonstration board on a PRO MATE II device programmer, or a PICSTART Plus development programmer, and easily test firmware. The MPLAB ICE in-circuit emulator may also be used with the PICDEM 2 demonstration board to test firmware. A prototype area has been provided to the user for adding additional hardware and connecting it to the microcontroller socket(s). Some of the features include a RS-232 interface, push button switches, a potentiometer for simulated analog input, a serial EEPROM to demonstrate usage of the I2CTM bus and separate headers for connection to an LCD module and a keypad.
16.10 PICSTART Plus Entry Level Development Programmer
The PICSTART Plus development programmer is an easy-to-use, low cost, prototype programmer. It connects to the PC via a COM (RS-232) port. MPLAB Integrated Development Environment software makes using the programmer simple and efficient. The PICSTART Plus development programmer supports all PICmicro devices with up to 40 pins. Larger pin count devices, such as the PIC16C92X and PIC17C76X, may be supported with an adapter socket. The PICSTART Plus development programmer is CE compliant.
2001 Microchip Technology Inc.
Advance Information
DS39582A-page 167
PIC16F87XA
16.13 PICDEM 3 Low Cost PIC16CXXX Demonstration Board
The PICDEM 3 demonstration board is a simple demonstration board that supports the PIC16C923 and PIC16C924 in the PLCC package. It will also support future 44-pin PLCC microcontrollers with an LCD Module. All the necessary hardware and software is included to run the basic demonstration programs. The user can program the sample microcontrollers provided with the PICDEM 3 demonstration board on a PRO MATE II device programmer, or a PICSTART Plus development programmer with an adapter socket, and easily test firmware. The MPLAB ICE in-circuit emulator may also be used with the PICDEM 3 demonstration board to test firmware. A prototype area has been provided to the user for adding hardware and connecting it to the microcontroller socket(s). Some of the features include a RS-232 interface, push button switches, a potentiometer for simulated analog input, a thermistor and separate headers for connection to an external LCD module and a keypad. Also provided on the PICDEM 3 demonstration board is a LCD panel, with 4 commons and 12 segments, that is capable of displaying time, temperature and day of the week. The PICDEM 3 demonstration board provides an additional RS-232 interface and Windows software for showing the demultiplexed LCD signals on a PC. A simple serial interface allows the user to construct a hardware demultiplexer for the LCD signals.
16.14 PICDEM 17 Demonstration Board
The PICDEM 17 demonstration board is an evaluation board that demonstrates the capabilities of several Microchip microcontrollers, including PIC17C752, PIC17C756A, PIC17C762 and PIC17C766. All necessary hardware is included to run basic demo programs, which are supplied on a 3.5-inch disk. A programmed sample is included and the user may erase it and program it with the other sample programs using the PRO MATE II device programmer, or the PICSTART Plus development programmer, and easily debug and test the sample code. In addition, the PICDEM 17 demonstration board supports downloading of programs to and executing out of external FLASH memory on board. The PICDEM 17 demonstration board is also usable with the MPLAB ICE in-circuit emulator, or the PICMASTER emulator and all of the sample programs can be run and modified using either emulator. Additionally, a generous prototype area is available for user hardware.
16.15 KEELOQ Evaluation and Programming Tools
KEELOQ evaluation and programming tools support Microchip's HCS Secure Data Products. The HCS evaluation kit includes a LCD display to show changing codes, a decoder to decode transmissions and a programming interface to program test transmitters.
DS39582A-page 168
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2001 Microchip Technology Inc.
24CXX/ 25CXX/ 93CXX
PIC14000
HCSXXX
PIC16C5X
PIC16C6X
PIC16C7X
PIC16C8X
PIC17C4X
PIC16F62X
PIC16C7XX
PIC16F8XX
PIC16C9XX
PIC17C7XX
PIC18CXX2
PIC12CXXX
PIC16CXXX
PIC18FXXX
MCRFXXX
MCP2510
TABLE 16-1:
MPLAB(R) Integrated Development Environment
9
9
9
9
9
9
9
9
9
9
9
9
9
99
99
MPLAB(R) C17 C Compiler
Software Tools
MPLAB(R) C18 C Compiler
MPASMTM Assembler/ MPLINKTM Object Linker
9
9
Programmers Debugger Emulators
Demo Boards and Eval Kits
2001 Microchip Technology Inc.
999
999
99
**
99
99
99
99
99
99
99
99
99
99
99
99
MPLAB(R) ICE In-Circuit Emulator
ICEPICTM In-Circuit Emulator
9
* *
9
9
9
9
9
9
9
MPLAB(R) ICD In-Circuit Debugger
9
**
9
9
9
PICSTART(R) Plus Entry Level Development Programmer
9
**
9
9
9
9
9
9
9
9
9
9
9
9
9
9
PRO MATE(R) II Universal Device Programmer
9
9
9
9
9
9
9
9
9
9
9
9
9
9
9
9
9
PICDEMTM 1 Demonstration Board
9

9
9
9
9
DEVELOPMENT TOOLS FROM MICROCHIP
Advance Information
9 9 9 9 9
PICDEMTM 2 Demonstration Board
9
9
PICDEMTM 3 Demonstration Board
PICDEMTM 14A Demonstration Board
PICDEMTM 17 Demonstration Board
KEELOQ(R) Evaluation Kit
99
KEELOQ(R) Transponder Kit
microIDTM Programmer's Kit
99
125 kHz microIDTM Developer's Kit
125 kHz Anticollision microIDTM Developer's Kit
9
13.56 MHz Anticollision microIDTM Developer's Kit
9
PIC16F87XA
DS39582A-page 169
MCP2510 CAN Developer's Kit
* Contact the Microchip Technology Inc. web site at www.microchip.com for information on how to use the MPLAB(R) ICD In-Circuit Debugger (DV164001) with PIC16C62, 63, 64, 65, 72, 73, 74, 76, 77. ** Contact Microchip Technology Inc. for availability date. Development tool is available on select devices.
9
PIC16F87XA
NOTES:
DS39582A-page 170
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PIC16F87XA
17.0 ELECTRICAL CHARACTERISTICS
Absolute Maximum Ratings Ambient temperature under bias................................................................................................................ .-55 to +125C Storage temperature .............................................................................................................................. -65C to +150C Voltage on any pin with respect to VSS (except VDD, MCLR. and RA4) ......................................... -0.3V to (VDD + 0.3V) Voltage on VDD with respect to VSS ............................................................................................................ -0.3 to +7.5V Voltage on MCLR with respect to VSS (Note 2) .................................................................................................0 to +14V Voltage on RA4 with respect to Vss ..................................................................................................................0 to +8.5V Total power dissipation (Note 1) ...............................................................................................................................1.0W Maximum current out of VSS pin ...........................................................................................................................300 mA Maximum current into VDD pin ..............................................................................................................................250 mA Input clamp current, IIK (VI < 0 or VI > VDD)..................................................................................................................... 20 mA Output clamp current, IOK (VO < 0 or VO > VDD) ............................................................................................................. 20 mA Maximum output current sunk by any I/O pin..........................................................................................................25 mA Maximum output current sourced by any I/O pin ....................................................................................................25 mA Maximum current sunk by PORTA, PORTB, and PORTE (combined) (Note 3) ...................................................200 mA Maximum current sourced by PORTA, PORTB, and PORTE (combined) (Note 3)..............................................200 mA Maximum current sunk by PORTC and PORTD (combined) (Note 3) .................................................................200 mA Maximum current sourced by PORTC and PORTD (combined) (Note 3) ............................................................200 mA Note 1: Power dissipation is calculated as follows: Pdis = VDD x {IDD - IOH} + {(VDD - VOH) x IOH} + (VOl x IOL) 2: Voltage spikes below VSS at the MCLR pin, inducing currents greater than 80 mA, may cause latch-up. Thus, a series resistor of 50-100 should be used when applying a "low" level to the MCLR pin, rather than pulling this pin directly to VSS. 3: PORTD and PORTE are not implemented on PIC16F873A/876A devices. NOTICE: Stresses above those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and functional operation of the device at those or any other conditions above those indicated in the operation listings of this specification is not implied. Exposure to maximum rating conditions for extended periods may affect device reliability.
2001 Microchip Technology Inc.
Advance Information
DS39582A-page 171
PIC16F87XA
FIGURE 17-1: PIC16F87XA VOLTAGE-FREQUENCY GRAPH 6.0 V 5.5 V 5.0 V PIC16F87XA
Voltage
4.5 V 4.0 V 3.5 V 3.0 V 2.5 V 2.0 V
20 MHz
Frequency
FIGURE 17-2:
PIC16LF87XA VOLTAGE-FREQUENCY GRAPH 6.0 V 5.5 V 5.0 V
Voltage
4.5 V 4.0 V 3.5 V 3.0 V 2.5 V 2.0 V PIC16LF87XA
4 MHz
10 MHz
Frequency
FMAX = (6.0 MHz/V) (VDDAPPMIN - 2.0V) + 4 MHz Note 1: VDDAPPMIN is the minimum voltage of the PICmicro(R) device in the application. Note 2: FMAX has a maximum frequency of 10 MHz.
DS39582A-page 172
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PIC16F87XA
17.1 DC Characteristics: PIC16F873A/874A/876A/877A (Industrial) PIC16LF873A/874A/876A/877A (Industrial)
Standard Operating Conditions (unless otherwise stated) Operating temperature -40C TA +85C for industrial Standard Operating Conditions (unless otherwise stated) Operating temperature -40C TA +85C for industrial Min Typ Max Units Conditions
PIC16LF873A/874A/876A/877A (Industrial) PIC16F873A/874A/876A/877A (Industrial) Param No. D001 D001 D001A D002 D003 VDR VPOR RAM Data Retention Voltage(1) VDD Start Voltage to ensure internal Power-on Reset signal VDD Rise Rate to ensure internal Power-on Reset signal Brown-out Reset Voltage Symbol VDD Characteristic/ Device Supply Voltage 16LF87XA 16F87XA
2.0 4.0 4.5 VBOR -- --
-- --
5.5 5.5 5.5 5.5
V V V V V V
LP, XT, RC osc configuration (DC to 4 MHz) LP, XT, RC osc configuration HS osc configuration BOR enabled, FMAX = 14 MHz(7)
1.5 VSS
-- --
See section on Power-on Reset for details
D004
SVDD
0.05
--
--
V/ms See section on Power-on Reset for details V BODEN bit in configuration word enabled
D005
VBOR
3.65
4.0
4.35
Legend: Rows with standard voltage device data only are shaded for improved readability. Data in "Typ" column is at 5V, 25C, unless otherwise stated. These parameters are for design guidance only, and are not tested. Note 1: This is the limit to which VDD can be lowered without losing RAM data. 2: The supply current is mainly a function of the operating voltage and frequency. Other factors, such as I/O pin loading, switching rate, oscillator type, internal code execution pattern and temperature also have an impact on the current consumption. The test conditions for all IDD measurements in active operation mode are: OSC1 = external square wave, from rail-to-rail; all I/O pins tri-stated, pulled to VDD; MCLR = VDD; WDT enabled/disabled as specified. 3: The power-down current in SLEEP mode does not depend on the oscillator type. Power-down current is measured with the part in SLEEP mode, with all I/O pins in hi-impedance state and tied to VDD and VSS. 4: For RC osc configuration, current through REXT is not included. The current through the resistor can be estimated by the formula Ir = VDD/2REXT (mA) with REXT in kOhm. 5: Timer1 oscillator (when enabled) adds approximately 20 A to the specification. This value is from characterization and is for design guidance only. This is not tested. 6: The current is the additional current consumed when this peripheral is enabled. This current should be added to the base IDD or IPD measurement. 7: When BOR is enabled, the device will operate correctly until the VBOR voltage trip point is reached.
2001 Microchip Technology Inc.
Advance Information
DS39582A-page 173
PIC16F87XA
17.1 DC Characteristics: PIC16F873A/874A/876A/877A (Industrial) PIC16LF873A/874A/876A/877A (Industrial) (Continued)
Standard Operating Conditions (unless otherwise stated) Operating temperature -40C TA +85C for industrial Standard Operating Conditions (unless otherwise stated) Operating temperature -40C TA +85C for industrial Min Typ Max Units Conditions
PIC16LF873A/874A/876A/877A (Industrial) PIC16F873A/874A/876A/877A (Industrial) Param No. D010 D010 D010A Symbol IDD Characteristic/ Device Supply Current(2,5) 16LF87XA 16F87XA 16LF87XA
-- -- --
0.6 1.6 20
2.0 4 35
mA mA A
XT, RC osc configuration FOSC = 4 MHz, VDD = 3.0V RC osc configurations FOSC = 4 MHz, VDD = 5.5V LP osc configuration FOSC = 32 kHz, VDD = 3.0V, WDT disabled HS osc configuration, FOSC = 20 MHz, VDD = 5.5V BOR enabled, VDD = 5.0V
D013 D015 IBOR
16F87XA Brown-out Reset Current(6)
-- --
7 85
15 200
mA A
Legend: Rows with standard voltage device data only are shaded for improved readability. Data in "Typ" column is at 5V, 25C, unless otherwise stated. These parameters are for design guidance only, and are not tested. Note 1: This is the limit to which VDD can be lowered without losing RAM data. 2: The supply current is mainly a function of the operating voltage and frequency. Other factors, such as I/O pin loading, switching rate, oscillator type, internal code execution pattern and temperature also have an impact on the current consumption. The test conditions for all IDD measurements in active operation mode are: OSC1 = external square wave, from rail-to-rail; all I/O pins tri-stated, pulled to VDD; MCLR = VDD; WDT enabled/disabled as specified. 3: The power-down current in SLEEP mode does not depend on the oscillator type. Power-down current is measured with the part in SLEEP mode, with all I/O pins in hi-impedance state and tied to VDD and VSS. 4: For RC osc configuration, current through REXT is not included. The current through the resistor can be estimated by the formula Ir = VDD/2REXT (mA) with REXT in kOhm. 5: Timer1 oscillator (when enabled) adds approximately 20 A to the specification. This value is from characterization and is for design guidance only. This is not tested. 6: The current is the additional current consumed when this peripheral is enabled. This current should be added to the base IDD or IPD measurement. 7: When BOR is enabled, the device will operate correctly until the VBOR voltage trip point is reached.
DS39582A-page 174
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PIC16F87XA
17.1 DC Characteristics: PIC16F873A/874A/876A/877A (Industrial) PIC16LF873A/874A/876A/877A (Industrial) (Continued)
Standard Operating Conditions (unless otherwise stated) Operating temperature -40C TA +85C for industrial Standard Operating Conditions (unless otherwise stated) Operating temperature -40C TA +85C for industrial Min Typ Max Units Conditions
PIC16LF873A/874A/876A/877A (Industrial) PIC16F873A/874A/876A/877A (Industrial) Param No. D020 D020 D021 D021 D021A D021A D023 IBOR Symbol IPD Characteristic/ Device Power-down Current(3,5) 16LF87XA 16F87XA 16LF87XA 16F87XA 16LF87XA 16F87XA Brown-out Reset Current(6)
-- -- -- --
7.5 10.5 0.9 1.5 0.9 1.5
30 42 5 16 5 19 200
A A A A A A A
VDD = 3.0V, WDT enabled, -40C to +85C VDD = 4.0V, WDT enabled, -40C to +85C VDD = 3.0V, WDT disabled, 0C to +70C VDD = 4.0V, WDT disabled, -40C to +85C VDD = 3.0V, WDT disabled, -40C to +85C VDD = 4.0V, WDT disabled, -40C to +85C BOR enabled, VDD = 5.0V
--
85
Legend: Rows with standard voltage device data only are shaded for improved readability. Data in "Typ" column is at 5V, 25C, unless otherwise stated. These parameters are for design guidance only, and are not tested. Note 1: This is the limit to which VDD can be lowered without losing RAM data. 2: The supply current is mainly a function of the operating voltage and frequency. Other factors, such as I/O pin loading, switching rate, oscillator type, internal code execution pattern and temperature also have an impact on the current consumption. The test conditions for all IDD measurements in active operation mode are: OSC1 = external square wave, from rail-to-rail; all I/O pins tri-stated, pulled to VDD; MCLR = VDD; WDT enabled/disabled as specified. 3: The power-down current in SLEEP mode does not depend on the oscillator type. Power-down current is measured with the part in SLEEP mode, with all I/O pins in hi-impedance state and tied to VDD and VSS. 4: For RC osc configuration, current through REXT is not included. The current through the resistor can be estimated by the formula Ir = VDD/2REXT (mA) with REXT in kOhm. 5: Timer1 oscillator (when enabled) adds approximately 20 A to the specification. This value is from characterization and is for design guidance only. This is not tested. 6: The current is the additional current consumed when this peripheral is enabled. This current should be added to the base IDD or IPD measurement. 7: When BOR is enabled, the device will operate correctly until the VBOR voltage trip point is reached.
2001 Microchip Technology Inc.
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DS39582A-page 175
PIC16F87XA
17.2 DC Characteristics: PIC16F873A/874A/876A/877A (Industrial) PIC16LF873A/874A/876A/877A (Industrial)
Standard Operating Conditions (unless otherwise stated) Operating temperature -40C TA +85C for industrial Operating voltage VDD range as described in DC specification (Section 17.1) Characteristic Input Low Voltage I/O ports with TTL buffer with Schmitt Trigger buffer MCLR, OSC1 (in RC mode) OSC1 (in XT and LP modes) OSC1 (in HS mode) Ports RC3 and RC4 with Schmitt Trigger buffer with SMBus Input High Voltage I/O ports with TTL buffer Min Typ Max Units Conditions
DC CHARACTERISTICS Param No.
Sym VIL
D030 D030A D031 D032 D033
Vss Vss Vss VSS VSS VSS Vss -0.5
D034 D034A VIH D040 D040A D041 D042 D042A D043 D044 D044A D070 IPURB IIL D060 D061 D063 *
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- 250
0.15VDD 0.8V 0.2VDD 0.2VDD 0.3V 0.3VDD 0.3VDD 0.6
V V V V V V V V
For entire VDD range 4.5V VDD 5.5V
(Note 1)
For entire VDD range for VDD = 4.5 to 5.5V
with Schmitt Trigger buffer MCLR OSC1 (in XT and LP modes) OSC1 (in HS mode) OSC1 (in RC mode) Ports RC3 and RC4 with Schmitt Trigger buffer with SMBus PORTB Weak Pull-up Current Input Leakage Current(2, 3) I/O ports MCLR, RA4/T0CKI OSC1
2.0 0.25VDD + 0.8V 0.8VDD 0.8VDD 1.6V 0.7VDD 0.9VDD 0.7VDD 1.4 50
VDD VDD VDD VDD VDD VDD VDD VDD 5.5 400
V V V V V V V V V A
4.5V VDD 5.5V For entire VDD range For entire VDD range (Note 1)
For entire VDD range for VDD = 4.5 to 5.5V VDD = 5V, VPIN = VSS, -40C TO +85C Vss VPIN VDD, Pin at hi-impedance Vss VPIN VDD Vss VPIN VDD, XT, HS and LP osc configuration
-- -- --
-- -- --
1 5 5
A A A
These parameters are characterized but not tested. Data in "Typ" column is at 5V, 25C unless otherwise stated. These parameters are for design guidance only and are not tested. Note 1: In RC oscillator configuration, the OSC1/CLKIN pin is a Schmitt Trigger input. It is not recommended that the PIC16F87XA be driven with external clock in RC mode. 2: The leakage current on the MCLR pin is strongly dependent on the applied voltage level. The specified levels represent normal operating conditions. Higher leakage current may be measured at different input voltages. 3: Negative current is defined as current sourced by the pin.
DS39582A-page 176
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PIC16F87XA
17.2 DC Characteristics: PIC16F873A/874A/876A/877A (Industrial) PIC16LF873A/874A/876A/877A (Industrial) (Continued)
Standard Operating Conditions (unless otherwise stated) Operating temperature -40C TA +85C for industrial Operating voltage VDD range as described in DC specification (Section 17.1) Characteristic Output Low Voltage I/O ports OSC2/CLKOUT (RC osc config) VOH D090 D092 D150* VOD Output High Voltage I/O ports(3) VDD - 0.7 -- -- -- -- -- 8.5 V V V IOH = -3.0 mA, VDD = 4.5V, -40C to +85C IOH = -1.3 mA, VDD = 4.5V, -40C to +85C RA4 pin Min Typ Max Units Conditions
DC CHARACTERISTICS Param No. D080 D083
Sym VOL
-- --
-- --
0.6 0.6
V V
IOL = 8.5 mA, VDD = 4.5V, -40C to +85C IOL = 1.6 mA, VDD = 4.5V, -40C to +85C
OSC2/CLKOUT (RC osc config) VDD - 0.7 Open-Drain High Voltage Capacitive Loading Specs on Output Pins COSC2 OSC2 pin --
D100
--
--
15
pF
In XT, HS and LP modes when external clock is used to drive OSC1
D101 D102 D120 D121 D122
CIO CB ED VDRW TDEW
All I/O pins and OSC2 (RC mode) SCL, SDA (I2C mode) Data EEPROM Memory Endurance VDD for read/write Erase/write cycle time Program FLASH Memory Endurance VDD for read VDD for erase/write
-- -- 100K VMIN -- 10K VMIN VMIN
-- -- 1M -- 4 100K -- --
50 400 -- 5.5 8 -- 5.5 5.5
pF pF E/W -40C to +85C V Using EECON to read/write VMIN = min. operating voltage ms E/W -40C to +85C V VMIN = min operating voltage V Using EECON to read/write, VMIN = min. operating voltage ms
D130 EP D131 VPR D132A D133 *
TPEW Erase/Write cycle time -- 4 8 These parameters are characterized but not tested. Data in "Typ" column is at 5V, 25C unless otherwise stated. These parameters are for design guidance only and are not tested. Note 1: In RC oscillator configuration, the OSC1/CLKIN pin is a Schmitt Trigger input. It is not recommended that the PIC16F87XA be driven with external clock in RC mode. 2: The leakage current on the MCLR pin is strongly dependent on the applied voltage level. The specified levels represent normal operating conditions. Higher leakage current may be measured at different input voltages. 3: Negative current is defined as current sourced by the pin.
2001 Microchip Technology Inc.
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DS39582A-page 177
PIC16F87XA
TABLE 17-1: COMPARATOR SPECIFICATIONS
Operating Conditions: 3.0V < VDD < 5.5V, -40C < TA < +85C, unless otherwise stated. Param No. D300 D301 D302 300 300A 301 * Characteristics Input Offset Voltage Input Common Mode Voltage* Response Time(1)* Comparator Mode Change to Output Valid* Sym VIOFF VICM TRESP TMC2OV Min -- 0 55 -- -- Typ 5.0 150 -- Max 10 VDD - 1.5 -- 400 600 10 Units mV V dB ns ns s PIC16F87XA PIC16LF87XA Comments
Common Mode Rejection Ratio* CMRR
These parameters are characterized but not tested. Note: Response time measured with one comparator input at (VDD - 1.5)/2 while the other input transitions from VSS to VDD.
TABLE 17-2:
VOLTAGE REFERENCE SPECIFICATIONS
Operating Conditions: 3.0V < VDD < 5.5V, -40C < TA < +85C, unless otherwise stated. Spec No. D310 D311 D312 310 * Characteristics Resolution Absolute Accuracy Unit Resistor Value (R)* Settling Time
(1)*
Sym VRES VRAA VRUR TSET
Min VDD/24 -- -- -- --
Typ -- -- -- 2k --
Max VDD/32 1/4 1/2 -- 10
Units LSb LSb LSb s
Comments
Low Range (VRR = `1') High Range (VRR = `0')
These parameters are characterized but not tested. Note: Settling time measured while VRR = 1 and VR<3:0> transitions from 0000 to 1111.
DS39582A-page 178
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PIC16F87XA
17.3 Timing Parameter Symbology
The timing parameter symbols have been created following one of the following formats: 1. TppS2ppS 2. TppS T F Frequency Lowercase letters (pp) and their meanings: pp cc CCP1 ck CLKOUT cs CS di SDI do SDO dt Data in io I/O port mc MCLR Uppercase letters and their meanings: S F Fall H High I Invalid (Hi-impedance) L Low I2C only AA BUF output access Bus free T Time 3. TCC:ST 4. Ts (I2C specifications only) (I2C specifications only)
osc rd rw sc ss t0 t1 wr
OSC1 RD RD or WR SCK SS T0CKI T1CKI WR
P R V Z High Low
Period Rise Valid Hi-impedance High Low
TCC:ST (I2C specifications only) CC HD Hold ST DAT DATA input hold STA START condition
SU STO
Setup STOP condition
FIGURE 17-3:
LOAD CONDITIONS
Load Condition 1 VDD/2 Load Condition 2
RL
Pin VSS RL CL = 464
CL
Pin VSS
CL
= 50 pF for all pins except OSC2, but including PORTD and PORTE outputs as ports, 15 pF for OSC2 output
Note: PORTD and PORTE are not implemented on PIC16F873A/876A devices.
2001 Microchip Technology Inc.
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DS39582A-page 179
PIC16F87XA
FIGURE 17-4: EXTERNAL CLOCK TIMING
Q4 Q1 Q2 Q3 Q4 Q1
OSC1 1 2 CLKOUT 3 3 4 4
TABLE 17-3:
Parameter No.
EXTERNAL CLOCK TIMING REQUIREMENTS
Sym Characteristic External CLKIN Frequency (Note 1) Min DC DC DC Oscillator Frequency (Note 1) DC 0.1 4 5 Typ -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- TCY -- -- -- -- -- -- Max 4 20 200 4 4 20 200 -- -- -- -- 10,000 250 250 -- DC -- -- -- 25 50 15 Units Conditions
FOSC
MHz XT and RC osc mode MHz HS osc mode kHz LP osc mode MHz RC osc mode MHz XT osc mode MHz HS osc mode kHz LP osc mode ns ns s ns ns ns ns s ns ns s ns ns ns ns XT and RC osc mode HS osc mode LP osc mode RC osc mode XT osc mode HS osc mode HS osc mode LP osc mode TCY = 4/FOSC XT oscillator LP oscillator HS oscillator XT oscillator LP oscillator HS oscillator
1
TOSC
External CLKIN Period (Note 1)
250 50 5 250 250 100 50 5
Oscillator Period (Note 1)
2 3
TCY TosL, TosH
Instruction Cycle Time (Note 1) External Clock in (OSC1) High or Low Time
200 100 2.5 15 -- -- --
4
TosR, TosF
External Clock in (OSC1) Rise or Fall Time
Data in "Typ" column is at 5V, 25C unless otherwise stated. These parameters are for design guidance only and are not tested. Note 1: Instruction cycle period (TCY) equals four times the input oscillator time-base period. All specified values are based on characterization data for that particular oscillator type under standard operating conditions, with the device executing code. Exceeding these specified limits may result in an unstable oscillator operation and/or higher than expected current consumption. All devices are tested to operate at "min." values with an external clock applied to the OSC1/CLKIN pin. When an external clock input is used, the "max." cycle time limit is "DC" (no clock) for all devices.
DS39582A-page 180
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PIC16F87XA
FIGURE 17-5: CLKOUT AND I/O TIMING
Q4 OSC1 10 CLKOUT 13 14 I/O Pin (Input) 17 I/O Pin (Output) Old Value 15 New Value 19 18 12 16 11 Q1 Q2 Q3
20, 21 Note: Refer to Figure 17-3 for load conditions.
TABLE 17-4:
Param No. 10* 11* 12* 13* 14* 15* 16* 17* 18* Symbol
CLKOUT AND I/O TIMING REQUIREMENTS
Characteristic OSC1 to CLKOUT Min -- -- -- -- -- TOSC + 200 0 -- Standard (F) Extended (LF) 100 200 0 -- -- -- -- TCY TCY Typ 75 75 35 35 -- -- -- 100 -- -- -- 10 -- 10 -- -- -- Max 200 200 100 100 0.5TCY + 20 -- -- 255 -- -- -- 40 145 40 145 -- -- Units Conditions ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns (Note 1) (Note 1) (Note 1) (Note 1) (Note 1) (Note 1) (Note 1)
TosH2ckL
TosH2ckH OSC1 to CLKOUT TckR TckF TckL2ioV TioV2ckH TckH2ioI TosH2ioV TosH2ioI CLKOUT rise time CLKOUT fall time CLKOUT to Port out valid Port in valid before CLKOUT Port in hold after CLKOUT OSC1 (Q1 cycle) to Port out valid OSC1 (Q2 cycle) to Port input invalid (I/O in hold time)
19* 20*
TioV2osH TioR
Port input valid to OSC1 (I/O in setup time) Port output rise time Standard (F) Extended (LF)
21*
TioF
Port output fall time
Standard (F) Extended (LF)
22* 23* *
Tinp Trbp
INT pin high or low time RB7:RB4 change INT high or low time
These parameters are characterized but not tested. Data in "Typ" column is at 5V, 25C unless otherwise stated. These parameters are for design guidance only and are not tested. These parameters are asynchronous events not related to any internal clock edges.
Note 1: Measurements are taken in RC mode where CLKOUT output is 4 x TOSC.
2001 Microchip Technology Inc.
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DS39582A-page 181
PIC16F87XA
FIGURE 17-6: RESET, WATCHDOG TIMER, OSCILLATOR START-UP TIMER AND POWER-UP TIMER TIMING
VDD MCLR Internal POR 33 PWRT Time-out OSC Time-out Internal Reset Watchdog Timer Reset 34 I/O Pins Note: Refer to Figure 17-3 for load conditions. 32 30
31 34
FIGURE 17-7:
BROWN-OUT RESET TIMING
VDD
VBOR 35
TABLE 17-5:
Parameter No. 30 31* 32 33* 34 35 *
RESET, WATCHDOG TIMER, OSCILLATOR START-UP TIMER, POWER-UP TIMER, AND BROWN-OUT RESET REQUIREMENTS
Characteristic MCLR Pulse Width (low) Watchdog Timer Time-out Period (No Prescaler) Oscillation Start-up Timer Period Power-up Timer Period I/O Hi-impedance from MCLR Low or Watchdog Timer Reset Brown-out Reset pulse width Min 2 7 -- 28 -- 100 Typ -- 18 1024 TOSC 72 -- -- Max -- 33 -- 132 2.1 -- Units
s
Symbol TMCL TWDT TOST TPWRT TIOZ TBOR
Conditions VDD = 5V, -40C to +85C VDD = 5V, -40C to +85C TOSC = OSC1 period VDD = 5V, -40C to +85C
ms -- ms
s s
VDD VBOR (D005)
These parameters are characterized but not tested. Data in "Typ" column is at 5V, 25C unless otherwise stated. These parameters are for design guidance only and are not tested.
DS39582A-page 182
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PIC16F87XA
FIGURE 17-8: TIMER0 AND TIMER1 EXTERNAL CLOCK TIMINGS
RA4/T0CKI
40
41
42
RC0/T1OSO/T1CKI
45
46
47 TMR0 or TMR1 Note: Refer to Figure 17-3 for load conditions.
48
TABLE 17-6:
Param No. 40* 41* 42* Symbol Tt0H Tt0L Tt0P
TIMER0 AND TIMER1 EXTERNAL CLOCK REQUIREMENTS
Characteristic T0CKI High Pulse Width T0CKI Low Pulse Width T0CKI Period No Prescaler With Prescaler No Prescaler With Prescaler No Prescaler With Prescaler Min 0.5TCY + 20 10 0.5TCY + 20 10 TCY + 40 Greater of: 20 or TCY + 40 N 0.5TCY + 20 15 25 30 50 0.5TCY + 20 15 25 30 50 Greater of: 30 OR TCY + 40 N Greater of: 50 OR TCY + 40 N 60 100 DC 2TOSC -- -- -- -- -- -- 200 7TOSC ns ns kHz -- Typ Max Units -- -- -- -- -- -- -- -- -- -- -- -- ns ns ns ns ns ns N = prescale value (2, 4,..., 256) Must also meet parameter 47 Conditions Must also meet parameter 42 Must also meet parameter 42
45*
Tt1H
T1CKI High Time Synchronous, Prescaler = 1 Synchronous, Standard(F) Prescaler = 2,4,8 Extended(LF) Asynchronous Standard(F) Extended(LF)
-- -- -- -- -- -- -- -- -- -- --
-- -- -- -- -- -- -- -- -- -- --
ns ns ns ns ns ns ns ns ns ns ns
46*
Tt1L
T1CKI Low Time
Synchronous, Prescaler = 1 Synchronous, Standard(F) Prescaler = 2,4,8 Extended(LF) Asynchronous Standard(F) Extended(LF) Standard(F)
Must also meet parameter 47
47*
Tt1P
T1CKI input period
Synchronous
N = prescale value (1, 2, 4, 8) N = prescale value (1, 2, 4, 8)
Extended(LF)
Asynchronous Ft1 48 *
Standard(F) Extended(LF)
Timer1 Oscillator Input Frequency Range (oscillator enabled by setting bit T1OSCEN)
TCKEZtmr1 Delay from external clock edge to timer increment
These parameters are characterized but not tested. Data in "Typ" column is at 5V, 25C unless otherwise stated. These parameters are for design guidance only and are not tested.
2001 Microchip Technology Inc.
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DS39582A-page 183
PIC16F87XA
FIGURE 17-9: CAPTURE/COMPARE/PWM TIMINGS (CCP1 AND CCP2)
RC1/T1OSI/CCP2 and RC2/CCP1 (Capture Mode) 50 52 51
RC1/T1OSI/CCP2 and RC2/CCP1 (Compare or PWM Mode) 53 Note: Refer to Figure 17-3 for load conditions. 54
TABLE 17-7:
Param No. 50* Sym TccL
CAPTURE/COMPARE/PWM REQUIREMENTS (CCP1 AND CCP2)
Characteristic CCP1 and CCP2 input low time No Prescaler Standard(F) With Prescaler Extended(LF) Min 0.5TCY + 20 10 20 0.5TCY + 20 Standard(F) With Prescaler Extended(LF) 10 20 3TCY + 40 N Standard(F) Extended(LF) -- -- -- -- Typ Max Units -- -- -- -- -- -- -- 10 25 10 25 -- -- -- -- -- -- -- 25 50 25 45 ns ns ns ns ns ns ns ns ns ns ns N = prescale value (1, 4 or 16) Conditions
51*
TccH
CCP1 and CCP2 input high time
No Prescaler
52* 53*
TccP TccR
CCP1 and CCP2 input period CCP1 and CCP2 output rise time
54*
TccF
CCP1 and CCP2 output fall time
Standard(F) Extended(LF)
*
These parameters are characterized but not tested. Data in "Typ" column is at 5V, 25C unless otherwise stated. These parameters are for design guidance only and are not tested.
DS39582A-page 184
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PIC16F87XA
FIGURE 17-10:
RE2/CS
PARALLEL SLAVE PORT TIMING (PIC16F874A/877A ONLY)
RE0/RD
RE1/WR
65 RD7:RD0 62 63 Note: Refer to Figure 17-3 for load conditions.
64
TABLE 17-8:
Parameter No. 62 63*
PARALLEL SLAVE PORT REQUIREMENTS (PIC16F874A/877A ONLY)
Symbol Characteristic Data in valid before WR or CS (setup time) WR or CS to data-in invalid (hold time) Standard(F) Extended(LF) Min Typ Max Units 20 20 35 -- 10 -- -- -- -- -- -- -- -- 80 30 ns ns ns ns ns Conditions
TdtV2wrH TwrH2dtI
64 65 *
TrdL2dtV TrdH2dtI
RD and CS to data-out valid RD or CS to data-out invalid
These parameters are characterized but not tested. Data in "Typ" column is at 5V, 25C unless otherwise stated. These parameters are for design guidance only and are not tested.
2001 Microchip Technology Inc.
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PIC16F87XA
FIGURE 17-11:
SS 70 SCK (CKP = 0) 71 72
SPI MASTER MODE TIMING (CKE = 0, SMP = 0)
78
79
SCK (CKP = 1) 79 78
80 SDO MSb 75, 76 SDI MSb IN 74 73 Note: Refer to Figure 17-3 for load conditions. BIT6 - - - -1
BIT6 - - - - - -1
LSb
LSb IN
FIGURE 17-12:
SPI MASTER MODE TIMING (CKE = 1, SMP = 1)
SS 81 SCK (CKP = 0) 71 73 SCK (CKP = 1) 80 78 72 79
SDO
MSb 75, 76
BIT6 - - - - - -1
LSb
SDI
MSb IN 74
BIT6 - - - -1
LSb IN
Note: Refer to Figure 17-3 for load conditions.
DS39582A-page 186
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PIC16F87XA
FIGURE 17-13:
SS 70 SCK (CKP = 0) 71 72 83
SPI SLAVE MODE TIMING (CKE = 0)
78
79
SCK (CKP = 1) 79 78
80 SDO MSb 75, 76 SDI MSb IN 74 73 Note: Refer to Figure 17-3 for load conditions. BIT6 - - - -1
BIT6 - - - - - -1
LSb 77 LSb IN
FIGURE 17-14:
SS
SPI SLAVE MODE TIMING (CKE = 1)
82
SCK (CKP = 0)
70 83 71 72
SCK (CKP = 1) 80
SDO
MSb 75, 76
BIT6 - - - - - -1
LSb 77
SDI
MSb IN 74
BIT6 - - - -1
LSb IN
Note: Refer to Figure 17-3 for load conditions.
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PIC16F87XA
TABLE 17-9:
Param No. 70* 71* 72* 73* 74* 75* 76* 77* 78* 79* 80* 81* 82* 83* *
SPI MODE REQUIREMENTS
Characteristic SS to SCK or SCK input SCK input high time (Slave mode) SCK input low time (Slave mode) Setup time of SDI data input to SCK edge Hold time of SDI data input to SCK edge SDO data output rise time SDO data output fall time SS to SDO output hi-impedance SCK output rise time (Master mode) Standard(F) Extended(LF) SCK output fall time (Master mode) SDO data output valid after SCK edge SDO data output setup to SCK edge SDO data output valid after SS edge SS after SCK edge Standard(F) Extended(LF) Standard(F) Extended(LF) Min Tcy TCY + 20 TCY + 20 100 100 -- -- -- 10 -- -- -- -- -- Tcy -- 1.5TCY + 40 Typ -- -- -- -- -- 10 25 10 -- 10 25 10 -- -- -- -- -- Max -- -- -- -- -- 25 50 25 50 25 50 25 50 145 -- 50 -- Units ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns Conditions
Symbol TssL2scH, TssL2scL TscH TscL TdiV2scH, TdiV2scL TscH2diL, TscL2diL TdoR TdoF TssH2doZ TscR TscF TscH2doV, TscL2doV TdoV2scH, TdoV2scL TssL2doV TscH2ssH, TscL2ssH
These parameters are characterized but not tested. Data in "Typ" column is at 5V, 25C unless otherwise stated. These parameters are for design guidance only and are not tested.
FIGURE 17-15:
I2C BUS START/STOP BITS TIMING
SCL 90 SDA
91 92
93
START Condition Note: Refer to Figure 17-3 for load conditions.
STOP Condition
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PIC16F87XA
TABLE 17-10: I2C BUS START/STOP BITS REQUIREMENTS
Parameter No. 90 Symbol Tsu:sta Characteristic START condition Setup time 91 Thd:sta START condition Hold time 92 Tsu:sto STOP condition Setup time 93 Thd:sto STOP condition Hold time 100 kHz mode 400 kHz mode 100 kHz mode 400 kHz mode 100 kHz mode 400 kHz mode 100 kHz mode 400 kHz mode Min 4700 600 4000 600 4700 600 4000 600 Typ Max -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- ns ns ns Units ns Conditions Only relevant for Repeated START condition After this period, the first clock pulse is generated
FIGURE 17-16:
I2C BUS DATA TIMING
103 100 101 102
SCL
90 91
106
107 92
SDA In 110 109 SDA Out Note: Refer to Figure 17-3 for load conditions. 109
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PIC16F87XA
TABLE 17-11: I2C BUS DATA REQUIREMENTS
Param No. 100 Sym THIGH Characteristic Clock high time 100 kHz mode 400 kHz mode SSP Module 101 TLOW Clock low time 100 kHz mode 400 kHz mode SSP Module 102 TR SDA and SCL rise time 100 kHz mode 400 kHz mode Min 4.0 0.6 0.5TCY 4.7 1.3 0.5TCY -- 20 + 0.1Cb -- 20 + 0.1Cb 4.7 0.6 4.0 0.6 0 0 250 100 4.7 0.6 -- -- 4.7 1.3 -- Max -- -- -- -- -- -- 1000 300 300 300 -- -- -- -- -- 0.9 -- -- -- -- 3500 -- -- -- 400 ns ns ns ns
s s s s s s
Units
s s
Conditions Device must operate at a minimum of 1.5 MHz Device must operate at a minimum of 10 MHz
Device must operate at a minimum of 1.5 MHz Device must operate at a minimum of 10 MHz
Cb is specified to be from 10 to 400 pF
103
TF
SDA and SCL fall time 100 kHz mode 400 kHz mode
Cb is specified to be from 10 to 400 pF Only relevant for Repeated START condition After this period, the first clock pulse is generated
90
Tsu:sta
START condition setup time
100 kHz mode 400 kHz mode
91
Thd:sta
START condition hold 100 kHz mode time 400 kHz mode Data input hold time 100 kHz mode 400 kHz mode
106
Thd:dat
ns
s
107
Tsu:dat
Data input setup time
100 kHz mode 400 kHz mode
ns ns
s s
(Note 2)
92
Tsu:sto
STOP condition setup 100 kHz mode time 400 kHz mode Output valid from clock Bus free time 100 kHz mode 400 kHz mode 100 kHz mode 400 kHz mode
109
TAA
ns ns
s s
(Note 1)
110
TBUF
Time the bus must be free before a new transmission can start
CB
Bus capacitive loading
pF
Note 1: As a transmitter, the device must provide this internal minimum delay time to bridge the undefined region (min. 300 ns) of the falling edge of SCL to avoid unintended generation of START or STOP conditions. 2: A fast mode (400 kHz) I2C bus device can be used in a standard mode (100 kHz) I2C bus system, but the requirement that Tsu:dat 250 ns must then be met. This will automatically be the case if the device does not stretch the LOW period of the SCL signal. If such a device does stretch the LOW period of the SCL signal, it must output the next data bit to the SDA line TR max.+ Tsu:dat = 1000 + 250 = 1250 ns (according to the standard mode I2C bus specification) before the SCL line is released.
DS39582A-page 190
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PIC16F87XA
FIGURE 17-17: USART SYNCHRONOUS TRANSMISSION (MASTER/SLAVE) TIMING
RC6/TX/CK Pin RC7/RX/DT Pin
121 121
120 122 Note: Refer to Figure 17-3 for load conditions.
TABLE 17-12: USART SYNCHRONOUS TRANSMISSION REQUIREMENTS
Param No. 120 Sym TckH2dtV Characteristic SYNC XMIT (MASTER & SLAVE) Clock high to data out valid Standard(F) -- Extended(LF) -- -- -- -- -- -- -- -- -- -- -- 80 100 45 50 45 50 ns ns ns ns ns ns Min Typ Max Units Conditions
121 122
Tckrf Tdtrf
Clock out rise time and fall time Standard(F) (Master mode) Extended(LF) Data out rise time and fall time Standard(F) Extended(LF)
Data in "Typ" column is at 5V, 25C unless otherwise stated. These parameters are for design guidance only and are not tested.
FIGURE 17-18:
USART SYNCHRONOUS RECEIVE (MASTER/SLAVE) TIMING
RC6/TX/CK pin RC7/RX/DT pin
125
126 Note: Refer to Figure 17-3 for load conditions.
TABLE 17-13: USART SYNCHRONOUS RECEIVE REQUIREMENTS
Parameter No. 125 126 Sym TdtV2ckL TckL2dtl Characteristic SYNC RCV (MASTER & SLAVE) Data setup before CK (DT setup time) Data hold after CK (DT hold time) Min Typ Max Units Conditions
15 15
-- --
-- --
ns ns
Data in "Typ" column is at 5V, 25C unless otherwise stated. These parameters are for design guidance only and are not tested.
2001 Microchip Technology Inc.
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PIC16F87XA
TABLE 17-14: A/D CONVERTER CHARACTERISTICS: PIC16F873A/874A/876A/877A (INDUSTRIAL) PIC16LF873A/874A/876A/877A (INDUSTRIAL)
Param No. A01 A03 A04 A06 A07 A10 A20 Sym NR EIL EDL EOFF EGN -- VREF Characteristic Resolution Integral linearity error Differential linearity error Offset error Gain error Monotonicity Reference voltage (VREF+ - VREF-) Min -- -- -- -- -- -- 2.0 Typ -- -- -- -- -- guaranteed(3) -- Max 10-bits <1 <1 <2 <1 -- VDD + 0.3 Units bit LSb LSb LSb LSb -- V Conditions VREF = VDD = 5.12V, VSS VAIN VREF VREF = VDD = 5.12V, VSS VAIN VREF VREF = VDD = 5.12V, VSS VAIN VREF VREF = VDD = 5.12V, VSS VAIN VREF VREF = VDD = 5.12V, VSS VAIN VREF VSS VAIN VREF Absolute minimum electrical spec. To ensure 10-bit accuracy.
A21 A22 A25 A30 A40
VREF+ Reference voltage High VREF- Reference voltage Low VAIN ZAIN IAD Analog input voltage Recommended impedance of analog voltage source A/D conversion current (VDD) Standard Extended
AVDD - 2.5V AVSS - 0.3V VSS - 0.3 V -- -- -- 10 -- -- 220 90 --
AVDD + 0.3V VREF+ - 2.0V VREF + 0.3 V 10.0 -- -- 1000
V V V k
A A A
Average current consumption when A/D is on (Note 1) During VAIN acquisition. Based on differential of VHOLD to VAIN to charge CHOLD, see Section 11.1. During A/D Conversion cycle
A50
IREF
VREF input current (Note 2)
-- *
--
10
A
These parameters are characterized but not tested. Data in "Typ" column is at 5V, 25C unless otherwise stated. These parameters are for design guidance only and are not tested.
Note 1: When A/D is off, it will not consume any current other than minor leakage current. The power-down current spec includes any such leakage from the A/D module. 2: VREF current is from RA3 pin or VDD pin, whichever is selected as reference input. 3: The A/D conversion result never decreases with an increase in the input voltage, and has no missing codes.
DS39582A-page 192
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PIC16F87XA
FIGURE 17-19: A/D CONVERSION TIMING
BSF ADCON0, GO (TOSC/2)(1) Q4 130 A/D CLK A/D DATA ADRES ADIF GO 132 9 8 7
... ...
1 TCY 131
2
1
0 NEW_DATA
OLD_DATA
DONE SAMPLING STOPPED
SAMPLE
Note: If the A/D clock source is selected as RC, a time of TCY is added before the A/D clock starts. This allows the SLEEP instruction to be executed.
TABLE 17-15: A/D CONVERSION REQUIREMENTS
Param No. 130 Sym TAD Characteristic A/D clock period Standard(F) Extended(LF) Standard(F) Extended(LF) 131 132 TCNV TACQ Conversion time (not including S/H time) (Note 1) Acquisition time (Note 2) 10* Min 1.6 3.0 2.0 3.0 Typ -- -- 4.0 6.0 -- 40 -- Max -- -- 6.0 9.0 12 -- -- Units
s s s s
Conditions TOSC based, VREF 3.0V TOSC based, VREF 2.0V A/D RC mode A/D RC mode
TAD
s s
The minimum time is the amplifier settling time. This may be used if the "new" input voltage has not changed by more than 1 LSb (i.e., 20.0 mV @ 5.12V) from the last sampled voltage (as stated on CHOLD). If the A/D clock source is selected as RC, a time of TCY is added before the A/D clock starts. This allows the SLEEP instruction to be executed.
134
TGO
Q4 to A/D clock start
--
TOSC/2
--
--
*
These parameters are characterized but not tested. Data in "Typ" column is at 5V, 25C unless otherwise stated. These parameters are for design guidance only and are not tested. This specification ensured by design.
Note 1: ADRES register may be read on the following TCY cycle. 2: See Section 11.1 for minimum conditions.
2001 Microchip Technology Inc.
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DS39582A-page 193
PIC16F87XA
NOTES:
DS39582A-page 194
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PIC16F87XA
18.0 DC AND AC CHARACTERISTICS GRAPHS AND TABLES
Graphs are not available at this time.
2001 Microchip Technology Inc.
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DS39582A-page 195
PIC16F87XA
NOTES:
DS39582A-page 196
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PIC16F87XA
19.0
19.1
PACKAGING INFORMATION
Package Marking Information
40-Lead PDIP
XXXXXXXXXXXXXXXXXX XXXXXXXXXXXXXXXXXX XXXXXXXXXXXXXXXXXX YYWWNNN
Example
PIC16F877A-/P 0112017
44-Lead TQFP
Example
XXXXXXXXXX XXXXXXXXXX XXXXXXXXXX YYWWNNN
PIC16F877A -/PT 0111017
44-Lead PLCC
Example
XXXXXXXXXX XXXXXXXXXX XXXXXXXXXX YYWWNNN
PIC16F877A -20/L 0103017
Legend:
XX...X Y YY WW NNN
Customer specific information* Year code (last digit of calendar year) Year code (last 2 digits of calendar year) Week code (week of January 1 is week `01') Alphanumeric traceability code
Note:
In the event the full Microchip part number cannot be marked on one line, it will be carried over to the next line thus limiting the number of available characters for customer specific information.
*
Standard PICmicro device marking consists of Microchip part number, year code, week code, and traceability code. For PICmicro device marking beyond this, certain price adders apply. Please check with your Microchip Sales Office. For QTP devices, any special marking adders are included in QTP price.
2001 Microchip Technology Inc.
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DS39582A-page 197
PIC16F87XA
Package Marking Information (Cont'd)
28-Lead PDIP (Skinny DIP)
XXXXXXXXXXXXXXXXX XXXXXXXXXXXXXXXXX YYWWNNN
Example
PIC16F876A-/SP 0117017
28-Lead SOIC
XXXXXXXXXXXXXXXXX XXXXXXXXXXXXXXXXX XXXXXXXXXXXXXXXXX YYWWNNN
Example
PIC16F876A-/SO
0110017
28-Lead SSOP
XXXXXXXXXXXX XXXXXXXXXXXX YYWWNNN
Example
PIC16F876A -/SO 0110017
28-Lead MLF
Example
XXXXXXXX XXXXXXXX YYWWNNN
1
PIC16F873A -I/ML 0112017
1
DS39582A-page 198
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PIC16F87XA
40-Lead Plastic Dual In-line (P) - 600 mil (PDIP)
E1
D
n E
2 1
A c
A2 L
A1 eB Units Dimension Limits n p INCHES* NOM 40 .100 .175 .150
B1 B p MILLIMETERS NOM 40 2.54 4.06 4.45 3.56 3.81 0.38 15.11 15.24 13.46 13.84 51.94 52.26 3.05 3.30 0.20 0.29 0.76 1.27 0.36 0.46 15.75 16.51 5 10 5 10
MIN
MAX
MIN
MAX
Number of Pins Pitch Top to Seating Plane A .160 .190 Molded Package Thickness A2 .140 .160 Base to Seating Plane .015 A1 Shoulder to Shoulder Width E .595 .600 .625 Molded Package Width E1 .530 .545 .560 Overall Length D 2.045 2.058 2.065 Tip to Seating Plane L .120 .130 .135 c Lead Thickness .008 .012 .015 Upper Lead Width B1 .030 .050 .070 Lower Lead Width B .014 .018 .022 Overall Row Spacing eB .620 .650 .680 5 10 15 Mold Draft Angle Top Mold Draft Angle Bottom 5 10 15 * Controlling Parameter Significant Characteristic Notes: Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed .010" (0.254mm) per side. JEDEC Equivalent: MO-011 Drawing No. C04-016
4.83 4.06 15.88 14.22 52.45 3.43 0.38 1.78 0.56 17.27 15 15
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DS39582A-page 199
PIC16F87XA
44-Lead Plastic Thin Quad Flatpack (PT) 10x10x1 mm Body, 1.0/0.10 mm Lead Form (TQFP)
E E1 #leads=n1 p
D1
D
B n
2 1
CH x 45 A
c
L
A1 (F)
A2
Number of Pins Pitch Pins per Side Overall Height Molded Package Thickness Standoff Foot Length Footprint (Reference) Foot Angle Overall Width Overall Length Molded Package Width Molded Package Length Lead Thickness Lead Width Pin 1 Corner Chamfer Mold Draft Angle Top Mold Draft Angle Bottom * Controlling Parameter Significant Characteristic
Units Dimension Limits n p n1 A A2 A1 L (F) E D E1 D1 c B CH
MIN
.039 .037 .002 .018 0 .463 .463 .390 .390 .004 .012 .025 5 5
INCHES NOM 44 .031 11 .043 .039 .004 .024 .039 3.5 .472 .472 .394 .394 .006 .015 .035 10 10
MAX
MIN
.047 .041 .006 .030 7 .482 .482 .398 .398 .008 .017 .045 15 15
MILLIMETERS* NOM 44 0.80 11 1.00 1.10 0.95 1.00 0.05 0.10 0.45 0.60 1.00 0 3.5 11.75 12.00 11.75 12.00 9.90 10.00 9.90 10.00 0.09 0.15 0.30 0.38 0.64 0.89 5 10 5 10
MAX
1.20 1.05 0.15 0.75 7 12.25 12.25 10.10 10.10 0.20 0.44 1.14 15 15
Notes: Dimensions D1 and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed .010" (0.254mm) per side. JEDEC Equivalent: MS-026 Drawing No. C04-076
DS39582A-page 200
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PIC16F87XA
44-Lead Plastic Leaded Chip Carrier (L) - Square (PLCC)
E E1 #leads=n1
D1 D
n12 CH2 x 45 CH1 x 45 A3 A2
35
A B1 B p D2
c
A1
E2 Units Dimension Limits n p INCHES* MIN NOM 44 .050 11 .165 .173 .145 .153 .020 .028 .024 .029 .040 .045 .000 .005 .685 .690 .685 .690 .650 .653 .650 .653 .590 .620 .590 .620 .008 .011 .026 .029 .013 .020 0 5 0 5
MAX
MIN
Number of Pins Pitch Pins per Side n1 Overall Height A .180 Molded Package Thickness .160 A2 Standoff A1 .035 A3 Side 1 Chamfer Height .034 Corner Chamfer 1 CH1 .050 Corner Chamfer (others) CH2 .010 Overall Width E .695 Overall Length D .695 Molded Package Width E1 .656 Molded Package Length D1 .656 Footprint Width E2 .630 Footprint Length .630 D2 c Lead Thickness .013 Upper Lead Width B1 .032 B .021 Lower Lead Width 10 Mold Draft Angle Top Mold Draft Angle Bottom 10 * Controlling Parameter Significant Characteristic Notes: Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed .010" (0.254mm) per side. JEDEC Equivalent: MO-047 Drawing No. C04-048
MILLIMETERS NOM 44 1.27 11 4.19 4.39 3.68 3.87 0.51 0.71 0.61 0.74 1.02 1.14 0.00 0.13 17.40 17.53 17.40 17.53 16.51 16.59 16.51 16.59 14.99 15.75 14.99 15.75 0.20 0.27 0.66 0.74 0.33 0.51 0 5 0 5
MAX
4.57 4.06 0.89 0.86 1.27 0.25 17.65 17.65 16.66 16.66 16.00 16.00 0.33 0.81 0.53 10 10
2001 Microchip Technology Inc.
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DS39582A-page 201
PIC16F87XA
28-Lead Skinny Plastic Dual In-line (SP) - 300 mil (PDIP)
E1
D
2 n 1
E
A2 A L A1 B1 B p
c
eB
Units Number of Pins Pitch Top to Seating Plane Molded Package Thickness Base to Seating Plane Shoulder to Shoulder Width Molded Package Width Overall Length Tip to Seating Plane Lead Thickness Upper Lead Width Lower Lead Width Overall Row Spacing Mold Draft Angle Top Mold Draft Angle Bottom Dimension Limits n p A A2 A1 E E1 D L c B1 B eB
INCHES* MIN NOM 28 .100 .140 .125 .015 .300 .275 1.345 .125 .008 .040 .016 .320 5 5 .310 .285 1.365 .130 .012 .053 .019 .350 10 10 .325 .295 1.385 .135 .015 .065 .022 .430 15 15 .150 .130 .160 .135 MAX MIN
MILLIMETERS NOM 28 2.54 3.56 3.18 0.38 7.62 6.99 34.16 3.18 0.20 1.02 0.41 8.13 5 5 7.87 7.24 34.67 3.30 0.29 1.33 0.48 8.89 10 10 8.26 7.49 35.18 3.43 0.38 1.65 0.56 10.92 15 15 3.81 3.30 4.06 3.43 MAX
* Controlling Parameter Significant Characteristic Notes: Dimension D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed .010" (0.254mm) per side. JEDEC Equivalent: MO-095
Drawing No. C04-070
DS39582A-page 202
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PIC16F87XA
28-Lead Plastic Small Outline (SO) - Wide, 300 mil (SOIC)
E E1 p
D
B n h 45 c A

2 1
A2
L Units Dimension Limits n p A A2 A1 E E1 D h L c B
A1 INCHES* NOM 28 .050 .099 .091 .008 .407 .295 .704 .020 .033 4 .011 .017 12 12 MILLIMETERS NOM 28 1.27 2.36 2.50 2.24 2.31 0.10 0.20 10.01 10.34 7.32 7.49 17.65 17.87 0.25 0.50 0.41 0.84 0 4 0.23 0.28 0.36 0.42 0 12 0 12
MIN
MAX
MIN
MAX
Number of Pins Pitch Overall Height Molded Package Thickness Standoff Overall Width Molded Package Width Overall Length Chamfer Distance Foot Length Foot Angle Top Lead Thickness Lead Width Mold Draft Angle Top Mold Draft Angle Bottom * Controlling Parameter Significant Characteristic
.093 .088 .004 .394 .288 .695 .010 .016 0 .009 .014 0 0
.104 .094 .012 .420 .299 .712 .029 .050 8 .013 .020 15 15
2.64 2.39 0.30 10.67 7.59 18.08 0.74 1.27 8 0.33 0.51 15 15
Notes: Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed .010" (0.254mm) per side. JEDEC Equivalent: MS-013 Drawing No. C04-052
2001 Microchip Technology Inc.
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DS39582A-page 203
PIC16F87XA
28-Lead Plastic Shrink Small Outline (SS) - 209 mil, 5.30 mm (SSOP)
E E1 p
D
B n 2 1
A c A2

A1
L
Number of Pins Pitch Overall Height Molded Package Thickness Standoff Overall Width Molded Package Width Overall Length Foot Length Lead Thickness Foot Angle Lead Width Mold Draft Angle Top Mold Draft Angle Bottom * Controlling Parameter Significant Characteristic
Units Dimension Limits n p A A2 A1 E E1 D L c B
MIN
.068 .064 .002 .299 .201 .396 .022 .004 0 .010 0 0
INCHES NOM 28 .026 .073 .068 .006 .309 .207 .402 .030 .007 4 .013 5 5
MAX
MIN
.078 .072 .010 .319 .212 .407 .037 .010 8 .015 10 10
MILLIMETERS* NOM MAX 28 0.65 1.73 1.85 1.98 1.63 1.73 1.83 0.05 0.15 0.25 7.59 7.85 8.10 5.11 5.25 5.38 10.06 10.20 10.34 0.56 0.75 0.94 0.10 0.18 0.25 0.00 101.60 203.20 0.25 0.32 0.38 0 5 10 0 5 10
Notes: Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed .010" (0.254mm) per side. JEDEC Equivalent: MS-150 Drawing No. C04-073
DS39582A-page 204
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PIC16F87XA
28-Lead Plastic Micro Leadframe Package (MF) 6x6 mm Body (MLF) -- Packaging
E E1 EXPOSED METAL PADS
Q D1 D D2 p 2 1 B
n R CH x 45 TOP VIEW
E2 L BOTTOM VIEW
A2 A1 A3 Units Dimension Limits Number of Pins Pitch Overall Height Molded Package Thickness Standoff Base Thickness Overall Width Molded Package Width Exposed Pad Width Overall Length Molded Package Length Exposed Pad Length Lead Width Lead Length Tie Bar Width Tie Bar Length Chamfer Mold Draft Angle Top *Controlling Parameter n p A A2 A1 A3 E E1 E2 D D1 D2 B L R Q CH .140 .009 .020 .005 .012 .009 .140 .000 MIN
A
INCHES NOM 28 .026 BSC .033 .026 .0004 .008 REF. .236 BSC .226 BSC .146 .236 BSC .226 BSC .146 .011 .024 .007 .016 .017 .152 .014 .030 .010 .026 .024 12 .152 .039 .031 .002 MAX MIN
MILLIMETERS* NOM 28 0.65 BSC 0.85 0.65 0.00 0.01 0.20 REF. 6.00 BSC 5.75 BSC 3.55 3.70 6.00 BSC 5.75 BSC 3.55 0.23 0.50 0.13 0.30 0.24 3.70 0.28 0.60 0.17 0.40 0.42 3.85 0.35 0.75 0.23 0.65 0.60 12 3.85 1.00 0.80 0.05 MAX
Notes: Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed .010" (0.254mm) per side. JEDEC equivalent: pending Drawing No. C04-114
2001 Microchip Technology Inc.
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DS39582A-page 205
PIC16F87XA
28-Lead Plastic Micro Leadframe Package (MF) 6x6 mm Body (MLF) -- Solder Pads
M
B
L M
p
SOLDER MASK
PACKAGE EDGE
Units Pitch Pad Width Pad Length Pad to Solder Mask *Controlling Parameter Drawing No. C04-2114 Dimension Limits p B L M MIN .009 .020 .005
INCHES NOM .026 BSC .011 .024 .014 .030 .006 MAX MIN
MILLIMETERS* NOM 0.65 BSC 0.23 0.50 0.13 0.28 0.60 0.35 0.75 0.15 MAX
DS39582A-page 206
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PIC16F87XA
APPENDIX A:
Version A Date
REVISION HISTORY
Revision Description
APPENDIX B:
DEVICE DIFFERENCES
11/2001 Original revision. The devices presented are enhanced versions of the PIC16F87X microcontrollers discussed in the "PIC16F87X Data Sheet" (DS30292).
The differences between the devices in this data sheet are listed in Table B-1.
TABLE B-1:
DIFFERENCES BETWEEN DEVICES IN THE PIC16F87XA FAMILY
PIC16F873A PIC16F874A 4K 192 128 15 Ports A,B,C,D,E MSSP, USART yes 8 input channels 40-pin PDIP 44-pin PLCC 44-pin QFP PIC16F876A 8K 368 256 14 Ports A,B,C MSSP, USART no 5 input channels 28-pin PDIP 28-pin SOIC 28-pin SSOP 28-pin MLF PIC16F877A 8K 368 256 15 Ports A,B,C,D,E MSSP, USART yes 8 input channels 40-pin PDIP 44-pin PLCC 44-pin QFP
FLASH Program Memory (14-bit words) Data Memory (bytes) EEPROM Data Memory (bytes) Interrupts I/O Ports Serial Communications Parallel Slave Port 10-bit Analog-to-Digital Module Packages
4K 192 128 14 Ports A,B,C MSSP, USART no 5 input channels 28-pin PDIP 28-pin SOIC 28-pin SSOP 28-pin MLF
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DS39582A-page 207
PIC16F87XA
APPENDIX C: CONVERSION CONSIDERATIONS
Considerations for converting from previous versions of devices to the ones listed in this data sheet are listed in Table C-1.
TABLE C-1:
CONVERSION CONSIDERATIONS
PIC16C7X 28/40 3 11 or 12 PSP, USART, SSP (SPI, I2C Slave) 20 MHz 2.5V - 5.5V 8-bit, 4 conversion clock selects 2 -- -- 4K, 8K EPROM PIC16F87X 28/40 3 13 or 14 PSP, USART, SSP (SPI, I2C Master/Slave) 20 MHz 2.2V - 5.5V 10-bit, 4 conversion clock selects 2 -- -- 4K, 8K FLASH (Erase/Write on single word) 192, 368 bytes 128, 256 bytes Segmented, starting at end of program memory On/Off PIC16F87XA 28/40 3 14 or 15 PSP, USART, SSP (SPI, I2C Master/Slave) 20 MHz 2.0V - 5.5V 10-bit, 7 conversion clock selects 2 2 yes 4K, 8K FLASH (Erase/Write on four-word blocks) 192, 368 bytes 128, 256 bytes On/Off Segmented, starting at beginning of program memory In-Circuit Debugger, Low Voltage Programming
Characteristic Pins Timers Interrupts Communication Frequency Voltage A/D CCP Comparator Comparator Voltage Reference Program Memory
RAM EEPROM data Code Protection Program Memory Write Protection Other
192, 368 bytes None On/Off --
In-Circuit Debugger, Low Voltage Programming
DS39582A-page 208
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PIC16F87XA
INDEX
A
A/D ................................................................................... 125 Acquisition Requirements ........................................ 128 ADCON0 Register .................................................... 125 ADCON1 Register .................................................... 125 ADIF bit .................................................................... 127 ADRESH Register .................................................... 125 ADRESL Register .................................................... 125 Analog Port Pins .................................................. 47, 49 Associated Registers and Bits ................................. 131 Calculating Acquisition Time .................................... 128 Configuring Analog Port Pins ................................... 129 Configuring the Interrupt .......................................... 127 Configuring the Module ............................................ 127 Conversion Clock ..................................................... 129 Conversions ............................................................. 130 Converter Characteristics ........................................ 192 Delays ...................................................................... 128 Effects of a RESET .................................................. 131 GO/DONE bit ........................................................... 127 Internal Sampling Switch (Rss) Impedance ............. 128 Operation During SLEEP ......................................... 131 Result Registers ....................................................... 130 Source Impedance ................................................... 128 Time Delays ............................................................. 128 A/D Conversion Requirements ......................................... 193 Absolute Maximum Ratings ............................................. 171 ACKSTAT ........................................................................... 99 ADCON0 Register .............................................................. 17 ADCON1 Register .............................................................. 18 Addressable Universal Synchronous Asynchronous Receiver Transmitter. See USART. ADRESH Register .............................................................. 17 ADRESL Register .............................................................. 18 Analog-to-Digital Converter. See A/D. Application Notes AN552 (Implementing Wake-up on Key Strokes Using PIC16CXXX) .................................... 42 AN556 (Implementing a Table Read) ........................ 28 Assembler MPASM Assembler .................................................. 165 Asynchronous Reception Associated Registers ....................................... 116, 118 Asynchronous Transmission Associated Registers ............................................... 114 Crystal/Ceramic Resonator Operation (HS, XT or LP Osc Configuration) ......................... 143 External Clock Input Operation (HS, XT or LP Osc Configuration) ......................... 143 Interrupt Logic .......................................................... 151 MSSP I2C Mode ........................................................... 78 MSSP (SPI Mode) ..................................................... 69 On-Chip RESET Circuit ........................................... 145 PIC16F873A/PIC16F876A Architecture ...................... 6 PIC16F874A/PIC16F877A Architecture ...................... 7 PORTC Peripheral Output Override (RC 0:2, 5:7) Pins .............................. 44 Peripheral Output Override (RC 3:4) Pins ..................................... 44 PORTD (in I/O Port Mode) ......................................... 46 PORTD and PORTE (Parallel Slave Port) ................. 49 PORTE (In I/O Port Mode) ......................................... 47 RA4/T0CKI Pin .......................................................... 40 RA5 Pin ..................................................................... 40 RB3:RB0 Port Pins .................................................... 42 RC Oscillator Mode .................................................. 144 Recommended MCLR Circuit .................................. 146 Simplified PWM Mode ............................................... 65 Timer0/WDT Prescaler .............................................. 51 Timer2 ....................................................................... 59 USART Receive ................................................115, 117 USART Transmit ...................................................... 113 Watchdog Timer ...................................................... 153 BOR. See Brown-out Reset. BRG. See Baud Rate Generator. BRGH Bit ......................................................................... 111 Brown-out Reset (BOR) .................... 141, 145, 146, 147, 148 BOR Status (BOR Bit) ............................................... 27 Bus Collision During a Repeated START Condition ................................................................. 106 Bus Collision During a START Condition ........................ 104 Bus Collision During a STOP Condition .......................... 107 Bus Collision Interrupt Flag bit, BCLIF ............................... 26 Bus Collision Timing for Transmit and Acknowledge ........................................................... 103
C
Capture/Compare/PWM (CCP) ......................................... 61 Associated Registers Capture, Compare and Timer1 .......................... 66 PWM and Timer2 ............................................... 67 Capture Mode ............................................................ 63 CCP1IF .............................................................. 63 Prescaler ........................................................... 63 CCP Timer Resources ............................................... 61 Compare Special Trigger Output of CCP1 ........................ 64 Special Trigger Output of CCP2 ........................ 64 Compare Mode .......................................................... 64 Software Interrupt Mode .................................... 64 Special Event Trigger ........................................ 64 Interaction of Two CCP Modules (Table) ................... 61 PWM Mode ................................................................ 65 Duty Cycle ......................................................... 65 Example Frequencies/Resolutions (Table) ........ 66 PWM Period ...................................................... 65 Special Event Trigger and A/D Conversions ............. 64
B
Banking, Data Memory ................................................. 14, 20 Baud Rate Generator ......................................................... 95 Associated Registers ............................................... 111 BCLIF ................................................................................. 26 BF ....................................................................................... 99 Block Diagram RA3:RA0 Port Pins .................................................... 39 Block Diagrams .................................................................. 56 A/D ........................................................................... 127 Analog Input Model .......................................... 128, 137 Baud Rate Generator ................................................. 95 Capture Mode Operation ........................................... 63 Comparator I/O Operating Modes ............................ 134 Comparator Output .................................................. 136 Comparator Voltage Reference ............................... 140 Compare Mode Operation ......................................... 64
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Capture/Compare/PWM Requirements (CCP1 and CCP2) .................................................... 184 CCP. See Capture/Compare/PWM. CCP1CON .......................................................................... 19 CCP1CON Register ........................................................... 17 CCP2CON .......................................................................... 19 CCP2CON Register ........................................................... 17 CCPR1H Register .................................................. 17, 19, 61 CCPR1L Register ................................................... 17, 19, 61 CCPR2H Register ........................................................ 17, 19 CCPR2L Register ......................................................... 17, 19 CCPxM0 bit ........................................................................ 62 CCPxM1 bit ........................................................................ 62 CCPxM2 bit ........................................................................ 62 CCPxM3 bit ........................................................................ 62 CCPxX bit ........................................................................... 62 CCPxY bit ........................................................................... 62 CLKOUT and I/O Timing Requirements ........................... 181 CMCON Register ............................................................... 18 Code Examples Call of a Subroutine in Page 1 from Page 0 ............... 28 Indirect Addressing .................................................... 29 Initializing PORTA ...................................................... 39 Loading the SSPBUF (SSPSR) Register ................... 72 Reading Data EEPROM ............................................. 33 Reading FLASH Program Memory ............................ 34 Saving STATUS, W and PCLATH Registers ........... 152 Writing to Data EEPROM ........................................... 33 Writing to FLASH Program Memory ........................... 36 Code Protection ....................................................... 141, 155 Comparator Module ......................................................... 133 Analog Input Connection Considerations ................. 137 Associated Registers ............................................... 138 Configuration ............................................................ 134 Effects of RESET ..................................................... 137 Interrupts .................................................................. 136 Operation ................................................................. 135 Operation During SLEEP ......................................... 137 Outputs ..................................................................... 135 Reference ................................................................. 135 Response Time ........................................................ 135 Comparator Voltage Reference ....................................... 139 Associated Registers ............................................... 140 Computed GOTO ............................................................... 28 Configuration Bits ............................................................. 141 Configuration Word .......................................................... 142 Conversion Considerations .............................................. 208 CVRCON Register ............................................................. 18 Data EEPROM Memory Associated Registers ................................................. 37 EEADR Register ........................................................ 31 EEADRH Register ..................................................... 31 EECON1 Register ...................................................... 31 EECON2 Register ...................................................... 31 Operation During Code Protect ................................. 37 Protection Against Spurious Writes ........................... 37 Reading ..................................................................... 33 Write Complete Flag (EEIF Bit) ................................. 31 Writing ........................................................................ 33 Data Memory ..................................................................... 14 Bank Select (RP1:RP0 Bits) .................................14, 20 General Purpose Registers ....................................... 14 Register File Map ..................................................15, 16 Special Function Registers ........................................ 17 DC and AC Characteristics Graphs and Tables .............. 195 DC Characteristics ....................................................173-177 Development Support ...................................................... 165 Device Differences ........................................................... 207 Device Overview .................................................................. 5 Direct Addressing ............................................................... 29
E
EEADR Register ...........................................................19, 31 EEADRH Register .........................................................19, 31 EECON1 Register .........................................................19, 31 EECON2 Register .........................................................19, 31 EEDATA Register .............................................................. 19 EEDATH Register .............................................................. 19 Electrical Characteristics .................................................. 171 Errata ................................................................................... 4 External Interrupt Input (RB0/INT). See Interrupt Sources. External Reference Signal ............................................... 135
F
Firmware Instructions ....................................................... 157 FLASH Program Memory Associated Registers ................................................. 37 EECON1 Register ...................................................... 31 EECON2 Register ...................................................... 31 Reading ..................................................................... 34 Writing ........................................................................ 35 FSR Register .................................................... 17, 18, 19, 29
G
General Call Address Support ........................................... 92
I
I/O Ports ............................................................................. 39 I2C Bus Data Requirements ............................................ 190 I2C Bus START/STOP Bits Requirements ....................... 189 I2C Mode Registers .................................................................... 78 I2C Mode ............................................................................ 78 ACK Pulse ............................................................82, 83 Acknowledge Sequence Timing .............................. 102 Baud Rate Generator ................................................. 95 Bus Collision Repeated START Condition ............................ 106 START Condition ............................................. 104 STOP Condition ............................................... 107 Clock Arbitration ........................................................ 96 Effect of a RESET .................................................... 103
D
Data EEPROM and FLASH Program Memory EEADR Register ........................................................ 31 EEADRH Register ...................................................... 31 EECON1 Register ...................................................... 31 EECON2 Register ...................................................... 31 EEDATA Register ...................................................... 31 EEDATH Register ...................................................... 31
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General Call Address Support ................................... 92 Master Mode .............................................................. 93 Operation ........................................................... 94 Repeated START Timing ................................... 98 Master Mode Reception ............................................. 99 Master Mode START Condition ................................. 97 Master Mode Transmission ........................................ 99 Multi-Master Communication, Bus Collision and Arbitration ......................................... 103 Multi-Master Mode ................................................... 103 Read/Write Bit Information (R/W Bit) ................... 82, 83 Serial Clock (RC3/SCK/SCL) ..................................... 83 Slave Mode ................................................................ 82 Addressing ......................................................... 82 Reception ........................................................... 83 Transmission ...................................................... 83 SLEEP Operation ..................................................... 103 STOP Condition Timing ........................................... 102 ICEPIC In-Circuit Emulator .............................................. 166 ID Locations ............................................................. 141, 155 In-Circuit Debugger .................................................. 141, 155 Resources ................................................................ 155 In-Circuit Serial Programming (ICSP) ...................... 141, 156 INDF ................................................................................... 19 INDF Register .........................................................17, 18, 29 Indirect Addressing ............................................................ 29 FSR Register ............................................................. 14 Instruction Format ............................................................ 157 Instruction Set .................................................................. 157 ADDLW .................................................................... 159 ADDWF .................................................................... 159 ANDLW .................................................................... 159 ANDWF .................................................................... 159 BCF .......................................................................... 159 BSF .......................................................................... 159 BTFSC ..................................................................... 159 BTFSS ..................................................................... 159 CALL ........................................................................ 160 CLRF ........................................................................ 160 CLRW ...................................................................... 160 CLRWDT .................................................................. 160 COMF ...................................................................... 160 DECF ....................................................................... 160 DECFSZ ................................................................... 161 GOTO ...................................................................... 161 INCF ......................................................................... 161 INCFSZ .................................................................... 161 IORLW ..................................................................... 161 IORWF ..................................................................... 161 MOVF ....................................................................... 162 MOVLW ................................................................... 162 MOVWF ................................................................... 162 NOP ......................................................................... 162 RETFIE .................................................................... 162 RETLW .................................................................... 162 RETURN .................................................................. 163 RLF .......................................................................... 163 RRF .......................................................................... 163 SLEEP ..................................................................... 163 SUBLW .................................................................... 163 SUBWF .................................................................... 163 SWAPF .................................................................... 164 XORLW .................................................................... 164 XORWF .................................................................... 164 Summary Table ........................................................ 158 INT Interrupt (RB0/INT). See Interrupt Sources. INTCON ............................................................................. 19 INTCON Register ............................................................... 22 GIE Bit ....................................................................... 22 INTE Bit ..................................................................... 22 INTF Bit ..................................................................... 22 PEIE Bit ..................................................................... 22 RBIE Bit ..................................................................... 22 RBIF Bit ................................................................22, 42 TMR0IE Bit ................................................................ 22 TMR0IF Bit ................................................................. 22 Inter-Integrated Circuit. See I2C. Internal Reference Signal ................................................ 135 Internal Sampling Switch (Rss) Impedance ..................... 128 Interrupt Sources ......................................................141, 151 Interrupt-on-Change (RB7:RB4 ) ............................... 42 RB0/INT Pin, External ..................................... 9, 11, 152 TMR0 Overflow ........................................................ 152 USART Receive/Transmit Complete ....................... 109 Interrupts Bus Collision Interrupt ................................................ 26 Synchronous Serial Port Interrupt .............................. 24 Interrupts, Context Saving During .................................... 152 Interrupts, Enable Bits Global Interrupt Enable (GIE Bit) ........................22, 151 Interrupt-on-Change (RB7:RB4) Enable (RBIE Bit) ............................................22, 152 Peripheral Interrupt Enable (PEIE Bit) ....................... 22 RB0/INT Enable (INTE Bit) ........................................ 22 TMR0 Overflow Enable (TMR0IE Bit) ........................ 22 Interrupts, Flag Bits Interrupt-on-Change (RB7:RB4) Flag (RBIF Bit) ...................................... 22, 42, 152 RB0/INT Flag (INTF Bit) ............................................ 22 TMR0 Overflow Flag (TMR0IF Bit) .....................22, 152
K
KEELOQ Evaluation and Programming Tools ................... 168
L
Loading of PC .................................................................... 28 Low Voltage ICSP Programming ..................................... 156 Low Voltage In-Circuit Serial Programming ..................... 141
M
Master Clear (MCLR) ........................................................... 8 MCLR Reset, Normal Operation ............... 145, 147, 148 MCLR Reset, SLEEP ................................ 145, 147, 148 Master Synchronous Serial Port (MSSP). See MSSP. Master Synchronous Serial Port. See MSSP MCLR ............................................................................... 146 MCLR/VPP ......................................................................... 10 Memory Organization ........................................................ 13 Data EEPROM Memory ............................................. 31 Data Memory ............................................................. 14 FLASH Program Memory .......................................... 31 Program Memory ....................................................... 13 MPLAB C17 and MPLAB C18 C Compilers .................... 165 MPLAB ICD In-Circuit Debugger ..................................... 167 MPLAB ICE High Performance Universal In-Circuit Emulator with MPLAB IDE ....................................... 166 MPLAB Integrated Development Environment Software .................................................................. 165 MPLINK Object Linker/MPLIB Object Librarian ............... 166
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MSSP ................................................................................. 69 I2C Mode. See I2C. SPI Mode ................................................................... 69 SPI Mode. See SPI MSSP Mode SPI Slave Mode ......................................................... 75 MSSP Module Clock Stretching ......................................................... 88 Clock Synchronization and the CKP Bit ..................... 89 Control Registers (General) ....................................... 69 Operation ................................................................... 82 Overview .................................................................... 69 SPI Master Mode ....................................................... 74 SSPBUF ..................................................................... 74 SSPSR ....................................................................... 74 Multi-Master Mode ........................................................... 103 PICDEM 2 Low Cost PIC16CXX Demonstration Board ............................................... 167 PICDEM 3 Low Cost PIC16CXXX Demonstration Board ............................................... 168 PICSTART Plus Entry Level Development Programmer ....................................... 167 PIE1 Register ................................................................18, 23 PIE2 Register ................................................................18, 25 Pinout Descriptions PIC16F873A/PIC16F876A ........................................... 8 PIR1 Register ...............................................................17, 24 PIR2 Register ...............................................................17, 26 POP ................................................................................... 28 POR. See Power-on Reset PORTA .....................................................................8, 10, 19 Associated Registers ................................................. 41 Functions ................................................................... 41 PORTA Register ...................................................17, 39 TRISA Register .......................................................... 39 PORTB .....................................................................9, 11, 19 Associated Registers ................................................. 43 Block Diagrams RB7:RB4 Port Pins ............................................ 42 Functions ................................................................... 43 PORTB Register ...................................................17, 42 RB0/INT Edge Select (INTEDG Bit) .......................... 21 RB0/INT Pin, External .....................................9, 11, 152 RB7:RB4 Interrupt-on-Change ................................ 152 RB7:RB4 Interrupt-on-Change Enable (RBIE Bit) ............................................22, 152 RB7:RB4 Interrupt-on-Change Flag (RBIF Bit) .....................................22, 42, 152 TRISB Register .....................................................19, 42 PORTB Register ................................................................ 19 PORTC .....................................................................9, 11, 19 Associated Registers ................................................. 45 Functions ................................................................... 45 PORTC Register ...................................................17, 44 RC3/SCK/SCL Pin ..................................................... 83 RC6/TX/CK Pin ........................................................ 110 RC7/RX/DT Pin .................................................110, 111 TRISC Register ...................................................44, 109 PORTD ...................................................................12, 19, 49 Associated Registers ................................................. 46 Functions ................................................................... 46 Parallel Slave Port (PSP) Function ............................ 46 PORTD Register ...................................................17, 46 TRISD Register .......................................................... 46 PORTE .........................................................................12, 19 Analog Port Pins ...................................................47, 49 Associated Registers ................................................. 48 Functions ................................................................... 47 Input Buffer Full Status (IBF Bit) ................................ 48 Input Buffer Overflow (IBOV Bit) ................................ 48 Output Buffer Full Status (OBF Bit) ........................... 48 PORTE Register ...................................................17, 47 PSP Mode Select (PSPMODE Bit) ........... 46, 47, 48, 49 RE0/RD/AN5 Pin ..................................................47, 49 RE1/WR/AN6 Pin ..................................................47, 49 RE2/CS/AN7 Pin ...................................................47, 49 TRISE Register .......................................................... 47 Postscaler, WDT Assignment (PSA Bit) ................................................ 21 Rate Select (PS2:PS0 Bits) ....................................... 21 Power-down Mode. See SLEEP.
N
nternal Reference Signal .................................................. 135
O
On-Line Support ............................................................... 217 OPCODE Field Descriptions ............................................ 157 OPTION_REG Register ..................................................... 21 INTEDG Bit ................................................................ 21 PS2:PS0 Bits .............................................................. 21 PSA Bit ....................................................................... 21 T0CS Bit ..................................................................... 21 T0SE Bit ..................................................................... 21 OSC1/CLKI Pin .................................................................. 10 OSC1/CLKIN Pin .................................................................. 8 OSC2/CLKOUT Pin ........................................................ 8, 10 Oscillator Configuration .................................................... 141 HS .................................................................... 143, 147 LP ..................................................................... 143, 147 RC ............................................................ 143, 144, 147 XT ..................................................................... 143, 147 Oscillator, WDT ................................................................ 153 Oscillators Capacitor Selection .................................................. 144 Ceramic Resonator Selection .................................. 143 Crystal and Ceramic Resonators ............................. 143 RC ............................................................................ 144
P
Package Marking Information .......................................... 197 Packaging Information ..................................................... 197 Paging, Program Memory .................................................. 28 Parallel Slave Port (PSP) ....................................... 12, 46, 49 Associated Registers ................................................. 50 Block Diagram ............................................................ 49 RE0/RD/AN5 Pin .................................................. 47, 49 RE1/WR/AN6 Pin ................................................. 47, 49 RE2/CS/AN7 Pin .................................................. 47, 49 Select (PSPMODE Bit) ..............................46, 47, 48, 49 Parallel Slave Port Requirements (PIC16F874A/877A Only) ........................................ 185 PCL Register .......................................................... 17, 18, 28 PCLATH Register ..............................................17, 18, 19, 28 PCON Register .................................................... 18, 27, 147 BOR Bit ...................................................................... 27 POR Bit ...................................................................... 27 PIC16F87XA Product Identification System ..................... 219 PICDEM 1 Low Cost PICmicro Demonstration Board ............................................... 167 PICDEM 17 Demonstration Board ................................... 168
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Power-on Reset (POR) ..................... 141, 145, 146, 147, 148 Oscillator Start-up Timer (OST) ....................... 141, 146 POR Status (POR Bit) ................................................ 27 Power Control (PCON) Register .............................. 147 Power-down (PD Bit) ......................................... 20, 145 Power-up Timer (PWRT) ................................. 141, 146 Time-out (TO Bit) ............................................... 20, 145 PR2 Register ................................................................ 18, 59 Prescaler, Timer0 Assignment (PSA Bit) ................................................ 21 Rate Select (PS2:PS0 Bits) ....................................... 21 PRO MATE II Universal Device Programmer .................. 167 Program Counter Reset Conditions ...................................................... 147 Program Memory ............................................................... 13 Interrupt Vector .......................................................... 13 Paging ........................................................................ 28 Program Memory Map and Stack (PIC16F873A/874A) .................................. 13 Program Memory Map and Stack (PIC16F876A/877A) .................................. 13 RESET Vector ............................................................ 13 Program Verification ......................................................... 155 Programming Pin (Vpp) ........................................................ 8 Programming, Device Instructions ................................... 157 PSP. See Parallel Slave Port. ............................................ 49 Pulse Width Modulation.See Capture/Compare/PWM, PWM Mode. PUSH ................................................................................. 28 RCSTA Register ...........................................................17, 19 ADDEN Bit ............................................................... 110 CREN Bit ................................................................. 110 FERR Bit .................................................................. 110 OERR Bit ................................................................. 110 RX9 Bit .................................................................... 110 RX9D Bit .................................................................. 110 SPEN Bit ...........................................................109, 110 SREN Bit ................................................................. 110 RD0/PSP0 Pin ................................................................... 12 RD1/PSP1 Pin ................................................................... 12 RD2/PSP2 Pin ................................................................... 12 RD3/PSP3 Pin ................................................................... 12 RD4/PSP4 Pin ................................................................... 12 RD5/PSP5 Pin ................................................................... 12 RD6/PSP6 Pin ................................................................... 12 RD7/PSP7 Pin ................................................................... 12 RE0/RD/AN5 Pin ............................................................... 12 RE1/WR/AN6 Pin ............................................................... 12 RE2/CS/AN7 Pin ................................................................ 12 Reader Response ............................................................ 218 Read-Modify-Write Operations ........................................ 157 Register File ....................................................................... 14 Register File Map (PIC16F873A/874A) ............................. 16 Register File Map (PIC16F876A/877A) ............................. 15 Registers ADCON0 (A/D Control 0) Register .......................... 125 ADCON1 (A/D Control 1) Register .......................... 126 CCP1CON/CCP2CON (CCP Control 1 and CCP Control 2) Register ............................ 62 CMCON (Comparator Control) Register .................. 133 CVRCON (Voltage Reference Control) Register ................................................... 139 EECON1 (EEPROM Control) Register ...................... 32 FSR ........................................................................... 29 INTCON Register ....................................................... 22 OPTION_REG Register ........................................21, 52 PCON (Power Control) Register ................................ 27 PIE1 (Peripheral Interrupt Enable 1) Register ........... 23 PIE2 (Peripheral Interrupt Enable 2) Register ........... 25 PIR1 (Peripheral Interrupt Request 1) Register ......... 24 PIR2 (Peripheral Interrupt Request 2) Register ......... 26 RCSTA (Receive Status and Control) Register ................................................... 110 Special Function, Summary ....................................... 17 SSPCON (MSSP Control) Register1 (I2C Mode) ................................................. 80 SSPCON (MSSP Control) Register1 (SPI Mode) ................................................ 71 SSPCON2 (MSSP Control) Register2 (I2C Mode) ................................................. 81 SSPSTAT (MSSP Status) Register (I2C Mode) ................................................. 79 SSPSTAT (MSSP Status) Register (SPI Mode) ................................................ 70 STATUS Register ...................................................... 20 T1CON (Timer1 Control) Register ............................. 55 T2CON (Timer2 Control Register) ............................. 59 TRISE Register .......................................................... 48 TXSTA (Transmit Status and Control) Register ....... 109 RESET ......................................................................141, 145 MCLR Reset. See MCLR.
R
RA0/AN0 Pin ........................................................................ 8 RA0/ANO Pin ..................................................................... 10 RA1/AN1 Pin .................................................................. 8, 10 RA2/AN2/VREF-/CVREF ...................................................... 10 RA2/AN2/VREF-/CVREF PIN .................................................. 8 RA3/AN3/VREF+ ................................................................. 10 RA3/AN3/VREF+ Pin ............................................................. 8 RA4/T0CKI/C1OUT Pin .................................................. 8, 10 RA5/SS/AN4/C2OUT Pin ............................................... 8, 10 RAM. See Data Memory. RB0/INT Pin ................................................................... 9, 11 RB1 Pin .......................................................................... 9, 11 RB2 Pin .......................................................................... 9, 11 RB3/PGM Pin ................................................................. 9, 11 RB4 Pin .......................................................................... 9, 11 RB5 Pin .......................................................................... 9, 11 RB6/PGC Pin ................................................................. 9, 11 RB7/PGD Pin ................................................................. 9, 11 RC0/T1OSO/T1CKI Pin ................................................. 9, 11 RC1/T1OSI/CCP2 Pin .................................................... 9, 11 RC2/CCP1 Pin ............................................................... 9, 11 RC3/SCK/SCL Pin ......................................................... 9, 11 RC4/SDI/SDA Pin .......................................................... 9, 11 RC5/SDO Pin ................................................................. 9, 11 RC6/TX/CK Pin .............................................................. 9, 11 RC7/RX/DT Pin .............................................................. 9, 11 RCREG .............................................................................. 19 RCREG Register ................................................................ 17
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Reset Brown-out Reset (BOR). See Brown-out Reset (BOR). Power-on Reset (POR). See Power-on Reset (POR). RESET Conditions for PCON Register .................... 147 RESET Conditions for Program Counter ................. 147 RESET Conditions for STATUS Register ................ 147 WDT Reset. See Watchdog Timer (WDT) RESET, Watchdog Timer, Oscillator Start-up Timer, Power-up Timer, and Brown-out Reset Requirements ................................................ 182 Revision History ............................................................... 207 STATUS Register C Bit ........................................................................... 20 DC Bit ........................................................................ 20 IRP Bit ........................................................................ 20 PD Bit ..................................................................20, 145 RP1:RP0 Bits ............................................................. 20 TO Bit ..................................................................20, 145 Z Bit ........................................................................... 20 Synchronous Master Reception Associated Registers ............................................... 121 Synchronous Master Transmission Associated Registers ............................................... 120 Synchronous Serial Port Interrupt ...................................... 24 Synchronous Slave Reception Associated Registers ............................................... 123 Synchronous Slave Transmission Associated Registers ............................................... 123
S
Sales and Support ............................................................ 219 SCI. See USART SCK .................................................................................... 69 SDI ..................................................................................... 69 SDO ................................................................................... 69 Serial Clock, SCK ............................................................... 69 Serial Communication Interface. See USART. Serial Data In, SDI ............................................................. 69 Serial Data Out, SDO ......................................................... 69 Serial Peripheral Interface. See SPI. Slave Select Synchronization ............................................. 75 Slave Select, SS ................................................................ 69 SLEEP .............................................................. 141, 145, 154 Software Simulator (MPLAB SIM) .................................... 166 SPBRG Register ................................................................ 18 Special Features of the CPU ............................................ 141 Special Function Registers ................................................ 17 Special Function Registers (SFRs) .................................... 17 Speed, Operating ................................................................. 1 SPI Mode ..................................................................... 69, 75 Associated Registers ................................................. 77 Bus Mode Compatibility ............................................. 77 Effects of a RESET .................................................... 77 Enabling SPI I/O ......................................................... 73 Master Mode .............................................................. 74 Master/Slave Connection ........................................... 73 Serial Clock ................................................................ 69 Serial Data In ............................................................. 69 Serial Data Out ........................................................... 69 Slave Select ............................................................... 69 Slave Select Synchronization ..................................... 75 SLEEP Operation ....................................................... 77 SPI Clock ................................................................... 74 Typical Connection ..................................................... 73 SPI Mode Requirements .................................................. 188 SS ...................................................................................... 69 SSP SPI Master/Slave Connection .................................... 73 SSPADD Register .............................................................. 18 SSPBUF ............................................................................. 19 SSPBUF Register .............................................................. 17 SSPCON Register .............................................................. 17 SSPCON2 Register ............................................................ 18 SSPIF ................................................................................. 24 SSPOV ............................................................................... 99 SSPSTAT Register ............................................................ 18 R/W Bit ................................................................. 82, 83 Stack .................................................................................. 28 Overflows ................................................................... 28 Underflow ................................................................... 28
T
T1CKPS0 bit ...................................................................... 55 T1CKPS1 bit ...................................................................... 55 T1CON ............................................................................... 19 T1CON Register ...........................................................17, 19 T1OSCEN bit ..................................................................... 55 T1SYNC bit ........................................................................ 55 T2CKPS0 bit ...................................................................... 59 T2CKPS1 bit ...................................................................... 59 T2CON Register ...........................................................17, 19 TAD ................................................................................... 129 Time-out Sequence ......................................................... 146 Timer0 ................................................................................ 51 Associated Registers ................................................. 53 Clock Source Edge Select (T0SE Bit) ....................... 21 Clock Source Select (T0CS Bit) ................................. 21 External Clock ............................................................ 52 Interrupt ..................................................................... 51 Overflow Enable (TMR0IE Bit) ................................... 22 Overflow Flag (TMR0IF Bit) ................................22, 152 Overflow Interrupt .................................................... 152 Prescaler .................................................................... 52 T0CKI ......................................................................... 52 Timer0 and Timer1 External Clock Requirements .......................................................... 183 Timer1 ...........................................................................55, 56 Associated Registers ................................................. 58 Asynchronous Counter Mode .................................... 57 Reading and Writing to ...................................... 57 Counter Operation ..................................................... 56 Operation in Timer Mode ........................................... 56 Oscillator .................................................................... 57 Capacitor Selection ............................................ 57 Prescaler .................................................................... 58 Resetting of Timer1 Registers ................................... 58 Resetting Timer1 using a CCP Trigger Output ........................................... 57 Synchronized Counter Mode ..................................... 56 TMR1H ...................................................................... 57 TMR1L ....................................................................... 57 Timer2 ................................................................................ 59 Associated Registers ................................................. 60 Output ........................................................................ 60 Postscaler .................................................................. 59 Prescaler .................................................................... 59 Timijg Diagrams SPI Master Mode (CKE = 1, SMP = 1) .................... 186
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Timing Diagrams .............................................................. 103 A/D Conversion ........................................................ 193 Acknowledge Sequence .......................................... 102 Asynchronous Master Transmission ........................ 114 Asynchronous Master Transmission (Back to Back) ......................................... 114 Asynchronous Reception ......................................... 116 Asynchronous Reception with Address Byte Frist ................................... 118 Asynchronous Reception with Address Detect ........................................ 118 Baud Rate Generator with Clock Arbitration .............. 96 BRG Reset Due to SDA Arbitration During START Condition ..................................... 105 Brown-out Reset ...................................................... 182 Bus Collision During a Repeated START Condition (Case 1) ................................... 106 Bus Collision During Repeated START Condition (Case 2) ................................... 106 Bus Collision During START Condition (SCL = 0) ................................................. 105 Bus Collision During START Condition (SDA Only) ............................................... 104 Bus Collision During STOP Condition (Case 1) ................................................... 107 Bus Collision During STOP Condition (Case 2) ................................................... 107 Capture/Compare/PWM (CCP1 and CCP2) ............ 184 CLKOUT and I/O ...................................................... 181 Clock Synchronization ............................................... 89 First START Bit Timing .............................................. 97 I2C Bus Data ............................................................ 189 I2C Bus START/STOP Bits ...................................... 188 I2C Master Mode (Reception, 7-bit Address) .......................................... 101 I2C Master Mode (Transmission, 7 or 10-bit Address) ........................................ 100 I2C Slave Mode Timing (Transmission, 10-bit Address) .......................................... 87 I2C Slave Mode Timing (Transmission, 7-bit Address) ............................................ 85 I2C Slave Mode Timing SEN = 1 (Reception, 10-bit Address) .......................................... 91 I2C Slave Mode Timing with SEN = 0 (Reception, 10-bit Address) ....................... 86 I2C Slave Mode Timing with SEN = 0 (Reception, 7-bit Address) ......................... 84 I2C Slave Mode Timing with SEN = 1 (Reception, 7-bit Address) ......................... 90 Parallel Slave Port (PSP) Read Waveforms ............................................... 50 Write Waveforms ............................................... 50 Parallel Slave Port Timing (PIC16F874A/877A Only) ........................ 185 Power-up Timer ....................................................... 182 Repeat START Condition .......................................... 98 RESET ..................................................................... 182 Slave Mode General Call Address Sequence (7 or 10-bit Address Mode) ........................ 92 Slave Synchronization ............................................... 75 Slow Rise Time (MCLR Tied to VDD via RC Network) ............................................ 150 SPI Master Mode (CKE = 0, SMP = 0) .................... 186 SPI Mode Timing (Master Mode) ............................... 74 SPI Mode Timing (Slave Mode with CKE = 0) ........... 76 SPI Mode Timing (Slave Mode with CKE = 1) ........... 76 SPI Slave Mode (CKE = 0) ...................................... 187 SPI Slave Mode (CKE = 1) ...................................... 187 Start-up Timer .......................................................... 182 STOP Condition Receive or Transmit Mode ............ 102 Synchronous Reception (Master Mode, SREN) ...... 122 Synchronous Transmission ..................................... 120 Synchronous Transmission (Through TXEN) .......... 120 Time-out Sequence on Power-up (MCLR Not Tied to VDD) Case 1 ............................................................. 150 Case 2 ............................................................. 150 Time-out Sequence on Power-up (MCLR Tied to VDD via RC Network) ............................... 149 Timer0 ..................................................................... 183 Timer1 ..................................................................... 183 USART Synchronous Receive (Master/Slave) ........ 191 USART Synchronous Transmission (Master/Slave) ......................................... 191 Wake-up from SLEEP via Interrupt .......................... 155 Watchdog Timer ...................................................... 182 TMR0 ................................................................................. 19 TMR0 Register ................................................................... 17 TMR1CS bit ....................................................................... 55 TMR1H .............................................................................. 19 TMR1H Register ................................................................ 17 TMR1L ............................................................................... 19 TMR1L Register ................................................................. 17 TMR1ON bit ....................................................................... 55 TMR2 ................................................................................. 19 TMR2 Register ................................................................... 17 TMR2ON bit ....................................................................... 59 TMRO Register .................................................................. 19 TOUTPS0 bit ..................................................................... 59 TOUTPS1 bit ..................................................................... 59 TOUTPS2 bit ..................................................................... 59 TOUTPS3 bit ..................................................................... 59 TRISA Register .................................................................. 18 TRISB Register .................................................................. 18 TRISC Register .................................................................. 18 TRISD Register .................................................................. 18 TRISE Register .............................................................18, 47 IBF Bit ........................................................................ 48 IBOV Bit ..................................................................... 48 OBF Bit ...................................................................... 48 PSPMODE Bit ........................................... 46, 47, 48, 49 TXREG .............................................................................. 19 TXREG Register ................................................................ 17 TXSTA Register ................................................................. 18 BRGH Bit ................................................................. 109 CSRC Bit ................................................................. 109 SYNC Bit ................................................................. 109 TRMT Bit .................................................................. 109 TX9 Bit ..................................................................... 109 TX9D Bit .................................................................. 109 TXEN Bit .................................................................. 109
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PIC16F87XA
U
USART ............................................................................. 109 Address Detect Enable (ADDEN Bit) ....................... 110 Asynchronous Mode ................................................ 113 Asynchronous Receive (9-bit Mode) ........................ 117 Asynchronous Receive with Address Detect. SeeAsynchronous Receive (9-bit Mode).. Asynchronous Receiver ........................................... 115 Asynchronous Reception ......................................... 116 Asynchronous Transmitter ....................................... 113 Baud Rate Generator (BRG) .................................... 111 Baud Rate Formula .......................................... 111 Baud Rates, Asynchronous Mode (BRGH = 0) ...................................... 112 Baud Rates, Asynchronous Mode (BRGH = 1) ...................................... 112 High Baud Rate Select (BRGH Bit) .................. 109 Sampling .......................................................... 111 Clock Source Select (CSRC Bit) .............................. 109 Continuous Receive Enable (CREN Bit) .................. 110 Framing Error (FERR Bit) ......................................... 110 Mode Select (SYNC Bit) ........................................... 109 Overrun Error (OERR Bit) ........................................ 110 Receive Data, 9th bit (RX9D Bit) .............................. 110 Receive Enable, 9-bit (RX9 Bit) ............................... 110 Serial Port Enable (SPEN Bit) .......................... 109, 110 Single Receive Enable (SREN Bit) .......................... 110 Synchronous Master Mode ...................................... 119 Synchronous Master Reception ............................... 121 Synchronous Master Transmission .......................... 119 Synchronous Slave Mode ........................................ 122 Synchronous Slave Reception ................................. 123 Synchronous Slave Transmit ................................... 122 Transmit Data, 9th Bit (TX9D) .................................. 109 Transmit Enable (TXEN Bit) ..................................... 109 Transmit Enable, Nine-bit (TX9 Bit) ......................... 109 Transmit Shift Register Status (TRMT Bit) ............... 109 USART Synchronous Receive Requirements .................. 191
V
VDD Pin ...........................................................................9, 12 VSS Pin ...........................................................................9, 12
W
Wake-up from SLEEP ...............................................141, 154 Interrupts ...........................................................147, 148 MCLR Reset ............................................................ 148 WDT Reset .............................................................. 148 Wake-Up Using Interrupts ................................................ 154 Watchdog Timer Register Summary ................................................... 153 Watchdog Timer (WDT) ............................................141, 153 Enable (WDTE Bit) .................................................. 153 Postscaler. See Postscaler, WDT Programming Considerations .................................. 153 RC Oscillator ............................................................ 153 Time-out Period ....................................................... 153 WDT Reset, Normal Operation .................145, 147, 148 WDT Reset, SLEEP ..................................145, 147, 148 WCOL ...................................................................97, 99, 102 WCOL Status Flag ............................................................. 97 WWW, On-Line Support ...................................................... 4
DS39582A-page 216
Advance Information
2001 Microchip Technology Inc.
PIC16F87XA
ON-LINE SUPPORT
Microchip provides on-line support on the Microchip World Wide Web (WWW) site. The web site is used by Microchip as a means to make files and information easily available to customers. To view the site, the user must have access to the Internet and a web browser, such as Netscape or Microsoft Explorer. Files are also available for FTP download from our FTP site.
Systems Information and Upgrade Hot Line
The Systems Information and Upgrade Line provides system users a listing of the latest versions of all of Microchip's development systems software products. Plus, this line provides information on how customers can receive any currently available upgrade kits.The Hot Line Numbers are: 1-800-755-2345 for U.S. and most of Canada, and 1-480-792-7302 for the rest of the world.
013001
Connecting to the Microchip Internet Web Site
The Microchip web site is available by using your favorite Internet browser to attach to: www.microchip.com The file transfer site is available by using an FTP service to connect to: ftp://ftp.microchip.com The web site and file transfer site provide a variety of services. Users may download files for the latest Development Tools, Data Sheets, Application Notes, User's Guides, Articles and Sample Programs. A variety of Microchip specific business information is also available, including listings of Microchip sales offices, distributors and factory representatives. Other data available for consideration is: * Latest Microchip Press Releases * Technical Support Section with Frequently Asked Questions * Design Tips * Device Errata * Job Postings * Microchip Consultant Program Member Listing * Links to other useful web sites related to Microchip Products * Conferences for products, Development Systems, technical information and more * Listing of seminars and events
2001 Microchip Technology Inc.
Advance Information
DS39582A-page 217
PIC16F87XA
READER RESPONSE
It is our intention to provide you with the best documentation possible to ensure successful use of your Microchip product. If you wish to provide your comments on organization, clarity, subject matter, and ways in which our documentation can better serve you, please FAX your comments to the Technical Publications Manager at (480) 792-4150. Please list the following information, and use this outline to provide us with your comments about this Data Sheet. To: RE: Technical Publications Manager Reader Response Total Pages Sent
From: Name Company Address City / State / ZIP / Country Telephone: (_______) _________ - _________ Application (optional): Would you like a reply? Device: PIC16F87XA Questions: 1. What are the best features of this document? Y N Literature Number: DS39582A FAX: (______) _________ - _________
2. How does this document meet your hardware and software development needs?
3. Do you find the organization of this data sheet easy to follow? If not, why?
4. What additions to the data sheet do you think would enhance the structure and subject?
5. What deletions from the data sheet could be made without affecting the overall usefulness?
6. Is there any incorrect or misleading information (what and where)?
7. How would you improve this document?
8. How would you improve our software, systems, and silicon products?
DS39582A-page 218
Advance Information
2001 Microchip Technology Inc.
PIC16F87XA
PIC16F87XA PRODUCT IDENTIFICATION SYSTEM
To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office. PART NO. Device X Temperature Range /XX Package XXX Pattern Examples:
a) b) Device PIC16F87XA(1), PIC16F87XAT(2); VDD range 4.0V to 5.5V PIC16LF87XA(1), PIC16LF87XAT(2 ); VDD range 2.0V to 5.5V c) PIC16F873A - I/P 301 = Industrial temp., PDIP package, normal VDD limits, QTP pattern #301. PIC16LF876A - I/SO = Industrial temp., SOIC package, Extended VDD limits. PIC16F877A - I/P = Industrial temp., PDIP package, 10MHz, normal VDD limits.
Temperature Range
I
=
-40C to
+85C (Industrial)
Package
ML PT SO SP P L
= = = = = =
MLF (Metal Lead Frame) TQFP (Thin Quad Flatpack) SOIC Skinny plastic DIP PDIP PLCC Note 1: 2: F = CMOS FLASH LF = Low Power CMOS FLASH T = in tape and reel - SOIC, PLCC, TQFP packages only.
Sales and Support
Data Sheets Products supported by a preliminary Data Sheet may have an errata sheet describing minor operational differences and recommended workarounds. To determine if an errata sheet exists for a particular device, please contact one of the following: 1. 2. 3. Your local Microchip sales office The Microchip Corporate Literature Center U.S. FAX: (480) 792-7277 The Microchip Worldwide Site (www.microchip.com)
Please specify which device, revision of silicon and Data Sheet (include Literature #) you are using. New Customer Notification System Register on our web site (www.microchip.com/cn) to receive the most current information on our products.
2001 Microchip Technology Inc.
Advance Information
DS39582A-page 219
M
WORLDWIDE SALES AND SERVICE
AMERICAS
Corporate Office
2355 West Chandler Blvd. Chandler, AZ 85224-6199 Tel: 480-792-7200 Fax: 480-792-7277 Technical Support: 480-792-7627 Web Address: http://www.microchip.com
ASIA/PACIFIC
Australia
Microchip Technology Australia Pty Ltd Suite 22, 41 Rawson Street Epping 2121, NSW Australia Tel: 61-2-9868-6733 Fax: 61-2-9868-6755
Japan
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Rocky Mountain
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China - Beijing
Microchip Technology Consulting (Shanghai) Co., Ltd., Beijing Liaison Office Unit 915 Bei Hai Wan Tai Bldg. No. 6 Chaoyangmen Beidajie Beijing, 100027, No. China Tel: 86-10-85282100 Fax: 86-10-85282104
Korea
Microchip Technology Korea 168-1, Youngbo Bldg. 3 Floor Samsung-Dong, Kangnam-Ku Seoul, Korea 135-882 Tel: 82-2-554-7200 Fax: 82-2-558-5934
Atlanta
500 Sugar Mill Road, Suite 200B Atlanta, GA 30350 Tel: 770-640-0034 Fax: 770-640-0307
Singapore
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Boston
2 Lan Drive, Suite 120 Westford, MA 01886 Tel: 978-692-3848 Fax: 978-692-3821
China - Chengdu
Microchip Technology Consulting (Shanghai) Co., Ltd., Chengdu Liaison Office Rm. 2401, 24th Floor, Ming Xing Financial Tower No. 88 TIDU Street Chengdu 610016, China Tel: 86-28-6766200 Fax: 86-28-6766599
Taiwan
Microchip Technology Taiwan 11F-3, No. 207 Tung Hua North Road Taipei, 105, Taiwan Tel: 886-2-2717-7175 Fax: 886-2-2545-0139
Chicago
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Dallas
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China - Fuzhou
Microchip Technology Consulting (Shanghai) Co., Ltd., Fuzhou Liaison Office Rm. 531, North Building Fujian Foreign Trade Center Hotel 73 Wusi Road Fuzhou 350001, China Tel: 86-591-7557563 Fax: 86-591-7557572
EUROPE
Denmark
Microchip Technology Nordic ApS Regus Business Centre Lautrup hoj 1-3 Ballerup DK-2750 Denmark Tel: 45 4420 9895 Fax: 45 4420 9910
Dayton
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Detroit
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China - Shanghai
Microchip Technology Consulting (Shanghai) Co., Ltd. Room 701, Bldg. B Far East International Plaza No. 317 Xian Xia Road Shanghai, 200051 Tel: 86-21-6275-5700 Fax: 86-21-6275-5060
France
Microchip Technology SARL Parc d'Activite du Moulin de Massy 43 Rue du Saule Trapu Batiment A - ler Etage 91300 Massy, France Tel: 33-1-69-53-63-20 Fax: 33-1-69-30-90-79
Kokomo
2767 S. Albright Road Kokomo, Indiana 46902 Tel: 765-864-8360 Fax: 765-864-8387
China - Shenzhen
Microchip Technology Consulting (Shanghai) Co., Ltd., Shenzhen Liaison Office Rm. 1315, 13/F, Shenzhen Kerry Centre, Renminnan Lu Shenzhen 518001, China Tel: 86-755-2350361 Fax: 86-755-2366086
Los Angeles
18201 Von Karman, Suite 1090 Irvine, CA 92612 Tel: 949-263-1888 Fax: 949-263-1338
Germany
Microchip Technology GmbH Gustav-Heinemann Ring 125 D-81739 Munich, Germany Tel: 49-89-627-144 0 Fax: 49-89-627-144-44
New York
150 Motor Parkway, Suite 202 Hauppauge, NY 11788 Tel: 631-273-5305 Fax: 631-273-5335
Hong Kong
Microchip Technology Hongkong Ltd. Unit 901-6, Tower 2, Metroplaza 223 Hing Fong Road Kwai Fong, N.T., Hong Kong Tel: 852-2401-1200 Fax: 852-2401-3431
Italy
Microchip Technology SRL Centro Direzionale Colleoni Palazzo Taurus 1 V. Le Colleoni 1 20041 Agrate Brianza Milan, Italy Tel: 39-039-65791-1 Fax: 39-039-6899883
San Jose
Microchip Technology Inc. 2107 North First Street, Suite 590 San Jose, CA 95131 Tel: 408-436-7950 Fax: 408-436-7955
India
Microchip Technology Inc. India Liaison Office Divyasree Chambers 1 Floor, Wing A (A3/A4) No. 11, O'Shaugnessey Road Bangalore, 560 025, India Tel: 91-80-2290061 Fax: 91-80-2290062
United Kingdom
Arizona Microchip Technology Ltd. 505 Eskdale Road Winnersh Triangle Wokingham Berkshire, England RG41 5TU Tel: 44 118 921 5869 Fax: 44-118 921-5820
10/01/01
Toronto
6285 Northam Drive, Suite 108 Mississauga, Ontario L4V 1X5, Canada Tel: 905-673-0699 Fax: 905-673-6509
DS39582A-page 220
Advance Information
2001 Microchip Technology Inc.

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